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fb289464f6
Add PVC's forcewake ranges. v2: - Drop replicated comment completely; move general cleanup of the documentation to a separate patch. Bspec: 67609 Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Stuart Summers <stuart.summers@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220511060228.1179450-3-matthew.d.roper@intel.com
350 lines
9.2 KiB
C
350 lines
9.2 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "../i915_selftest.h"
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static int intel_fw_table_check(const struct intel_forcewake_range *ranges,
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unsigned int num_ranges,
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bool is_watertight)
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{
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unsigned int i;
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s32 prev;
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for (i = 0, prev = -1; i < num_ranges; i++, ranges++) {
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/* Check that the table is watertight */
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if (is_watertight && (prev + 1) != (s32)ranges->start) {
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pr_err("%s: entry[%d]:(%x, %x) is not watertight to previous (%x)\n",
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__func__, i, ranges->start, ranges->end, prev);
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return -EINVAL;
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}
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/* Check that the table never goes backwards */
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if (prev >= (s32)ranges->start) {
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pr_err("%s: entry[%d]:(%x, %x) is less than the previous (%x)\n",
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__func__, i, ranges->start, ranges->end, prev);
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return -EINVAL;
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}
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/* Check that the entry is valid */
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if (ranges->start >= ranges->end) {
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pr_err("%s: entry[%d]:(%x, %x) has negative length\n",
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__func__, i, ranges->start, ranges->end);
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return -EINVAL;
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}
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prev = ranges->end;
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}
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return 0;
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}
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static int intel_shadow_table_check(void)
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{
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struct {
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const struct i915_range *regs;
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unsigned int size;
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} range_lists[] = {
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{ gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
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{ gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
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{ gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) },
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{ dg2_shadowed_regs, ARRAY_SIZE(dg2_shadowed_regs) },
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{ pvc_shadowed_regs, ARRAY_SIZE(pvc_shadowed_regs) },
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};
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const struct i915_range *range;
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unsigned int i, j;
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s32 prev;
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for (j = 0; j < ARRAY_SIZE(range_lists); ++j) {
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range = range_lists[j].regs;
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for (i = 0, prev = -1; i < range_lists[j].size; i++, range++) {
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if (range->end < range->start) {
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pr_err("%s: range[%d]:(%06x-%06x) has end before start\n",
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__func__, i, range->start, range->end);
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return -EINVAL;
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}
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if (prev >= (s32)range->start) {
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pr_err("%s: range[%d]:(%06x-%06x) is before end of previous (%06x)\n",
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__func__, i, range->start, range->end, prev);
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return -EINVAL;
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}
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if (range->start % 4) {
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pr_err("%s: range[%d]:(%06x-%06x) has non-dword-aligned start\n",
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__func__, i, range->start, range->end);
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return -EINVAL;
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}
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prev = range->end;
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}
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}
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return 0;
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}
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int intel_uncore_mock_selftests(void)
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{
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struct {
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const struct intel_forcewake_range *ranges;
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unsigned int num_ranges;
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bool is_watertight;
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} fw[] = {
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{ __vlv_fw_ranges, ARRAY_SIZE(__vlv_fw_ranges), false },
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{ __chv_fw_ranges, ARRAY_SIZE(__chv_fw_ranges), false },
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{ __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
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{ __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
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{ __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
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{ __xehp_fw_ranges, ARRAY_SIZE(__xehp_fw_ranges), true },
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{ __pvc_fw_ranges, ARRAY_SIZE(__pvc_fw_ranges), true },
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};
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int err, i;
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for (i = 0; i < ARRAY_SIZE(fw); i++) {
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err = intel_fw_table_check(fw[i].ranges,
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fw[i].num_ranges,
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fw[i].is_watertight);
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if (err)
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return err;
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}
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err = intel_shadow_table_check();
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if (err)
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return err;
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return 0;
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}
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static int live_forcewake_ops(void *arg)
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{
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static const struct reg {
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const char *name;
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u8 min_graphics_ver;
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u8 max_graphics_ver;
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unsigned long platforms;
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unsigned int offset;
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} registers[] = {
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{
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"RING_START",
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6, 7,
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0x38,
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},
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{
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"RING_MI_MODE",
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8, U8_MAX,
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0x9c,
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}
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};
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const struct reg *r;
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struct intel_gt *gt = arg;
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struct intel_uncore_forcewake_domain *domain;
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struct intel_uncore *uncore = gt->uncore;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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intel_wakeref_t wakeref;
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unsigned int tmp;
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int err = 0;
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GEM_BUG_ON(gt->awake);
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/* vlv/chv with their pcu behave differently wrt reads */
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if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) {
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pr_debug("PCU fakes forcewake badly; skipping\n");
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return 0;
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}
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/*
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* Not quite as reliable across the gen as one would hope.
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*
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* Either our theory of operation is incorrect, or there remain
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* external parties interfering with the powerwells.
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*
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* https://bugs.freedesktop.org/show_bug.cgi?id=110210
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*/
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if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN))
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return 0;
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/* We have to pick carefully to get the exact behaviour we need */
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for (r = registers; r->name; r++)
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if (IS_GRAPHICS_VER(gt->i915, r->min_graphics_ver, r->max_graphics_ver))
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break;
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if (!r->name) {
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pr_debug("Forcewaked register not known for %s; skipping\n",
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intel_platform_name(INTEL_INFO(gt->i915)->platform));
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return 0;
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}
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wakeref = intel_runtime_pm_get(uncore->rpm);
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for_each_fw_domain(domain, uncore, tmp) {
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smp_store_mb(domain->active, false);
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if (!hrtimer_cancel(&domain->timer))
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continue;
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intel_uncore_fw_release_timer(&domain->timer);
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}
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for_each_engine(engine, gt, id) {
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i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset);
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u32 __iomem *reg = uncore->regs + engine->mmio_base + r->offset;
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enum forcewake_domains fw_domains;
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u32 val;
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if (!engine->default_state)
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continue;
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fw_domains = intel_uncore_forcewake_for_reg(uncore, mmio,
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FW_REG_READ);
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if (!fw_domains)
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continue;
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for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
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if (!domain->wake_count)
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continue;
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pr_err("fw_domain %s still active, aborting test!\n",
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intel_uncore_forcewake_domain_to_str(domain->id));
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err = -EINVAL;
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goto out_rpm;
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}
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intel_uncore_forcewake_get(uncore, fw_domains);
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val = readl(reg);
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intel_uncore_forcewake_put(uncore, fw_domains);
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/* Flush the forcewake release (delayed onto a timer) */
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for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
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smp_store_mb(domain->active, false);
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if (hrtimer_cancel(&domain->timer))
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intel_uncore_fw_release_timer(&domain->timer);
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preempt_disable();
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err = wait_ack_clear(domain, FORCEWAKE_KERNEL);
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preempt_enable();
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if (err) {
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pr_err("Failed to clear fw_domain %s\n",
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intel_uncore_forcewake_domain_to_str(domain->id));
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goto out_rpm;
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}
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}
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if (!val) {
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pr_err("%s:%s was zero while fw was held!\n",
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engine->name, r->name);
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err = -EINVAL;
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goto out_rpm;
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}
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/* We then expect the read to return 0 outside of the fw */
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if (wait_for(readl(reg) == 0, 100)) {
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pr_err("%s:%s=%0x, fw_domains 0x%x still up after 100ms!\n",
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engine->name, r->name, readl(reg), fw_domains);
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err = -ETIMEDOUT;
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goto out_rpm;
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}
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}
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out_rpm:
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intel_runtime_pm_put(uncore->rpm, wakeref);
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return err;
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}
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static int live_forcewake_domains(void *arg)
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{
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#define FW_RANGE 0x40000
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struct intel_gt *gt = arg;
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struct intel_uncore *uncore = gt->uncore;
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unsigned long *valid;
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u32 offset;
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int err;
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if (!HAS_FPGA_DBG_UNCLAIMED(gt->i915) &&
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!IS_VALLEYVIEW(gt->i915) &&
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!IS_CHERRYVIEW(gt->i915))
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return 0;
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/*
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* This test may lockup the machine or cause GPU hangs afterwards.
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*/
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if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN))
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return 0;
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valid = bitmap_zalloc(FW_RANGE, GFP_KERNEL);
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if (!valid)
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return -ENOMEM;
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intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
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check_for_unclaimed_mmio(uncore);
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for (offset = 0; offset < FW_RANGE; offset += 4) {
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i915_reg_t reg = { offset };
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intel_uncore_posting_read_fw(uncore, reg);
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if (!check_for_unclaimed_mmio(uncore))
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set_bit(offset, valid);
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}
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intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
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err = 0;
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for_each_set_bit(offset, valid, FW_RANGE) {
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i915_reg_t reg = { offset };
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iosf_mbi_punit_acquire();
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intel_uncore_forcewake_reset(uncore);
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iosf_mbi_punit_release();
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check_for_unclaimed_mmio(uncore);
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intel_uncore_posting_read_fw(uncore, reg);
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if (check_for_unclaimed_mmio(uncore)) {
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pr_err("Unclaimed mmio read to register 0x%04x\n",
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offset);
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err = -EINVAL;
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}
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}
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bitmap_free(valid);
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return err;
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}
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static int live_fw_table(void *arg)
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{
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struct intel_gt *gt = arg;
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/* Confirm the table we load is still valid */
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return intel_fw_table_check(gt->uncore->fw_domains_table,
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gt->uncore->fw_domains_table_entries,
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GRAPHICS_VER(gt->i915) >= 9);
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}
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int intel_uncore_live_selftests(struct drm_i915_private *i915)
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{
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static const struct i915_subtest tests[] = {
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SUBTEST(live_fw_table),
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SUBTEST(live_forcewake_ops),
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SUBTEST(live_forcewake_domains),
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};
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return intel_gt_live_subtests(tests, to_gt(i915));
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}
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