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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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de88aa67af
Add the Gaudi2 code to initialize the ASIC's profiler. The profile receives its initialization values from the user, same as in Gaudi2, but the code to initialize is in the driver because the configuration space of the device is not directly exposed to the user. Signed-off-by: Benjamin Dotan <bdotan@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
1063 lines
28 KiB
C
1063 lines
28 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2020 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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#ifndef GAUDI2_CORESIGHT_REGS_DRV_H_
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#define GAUDI2_CORESIGHT_REGS_DRV_H_
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#include "gaudi2_masks.h"
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#include "../include/gaudi2/gaudi2_coresight.h"
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#include "gaudi2P.h"
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/* FUNNEL Offsets - same offsets for all funnels*/
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#define mmFUNNEL_CTRL_REG_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_CTRL_REG - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_PRIORITY_CTRL_REG_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_PRIORITY_CTRL_REG - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_ITATBDATA0_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_ITATBDATA0 - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_ITATBCTR2_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR2 - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_ITATBCTR1_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR1 - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_ITATBCTR0_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR0 - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_ITCTRL_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_ITCTRL - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_CLAIMSET_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_CLAIMSET - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_CLAIMCLR_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_CLAIMCLR - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_LOCKACCESS_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_LOCKACCESS - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_LOCKSTATUS_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_LOCKSTATUS - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_AUTHSTATUS_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_AUTHSTATUS - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_DEVID_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_DEVID - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_DEVTYPE_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_DEVTYPE - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_PIDR4_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_PIDR4 - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_PERIPHID5_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_PERIPHID5 - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_PERIPHID6_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_PERIPHID6 - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_PERIPHID7_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_PERIPHID7 - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_PIDR0_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_PIDR0 - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_PIDR1_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_PIDR1 - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_PIDR2_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_PIDR2 - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_PIDR3_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_PIDR3 - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_CID0_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_CID0 - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_CID1_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_CID1 - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_CID2_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_CID2 - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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#define mmFUNNEL_CID3_OFFSET \
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(mmDCORE0_TPC0_EML_FUNNEL_CID3 - \
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mmDCORE0_TPC0_EML_FUNNEL_BASE)
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/* ETF Offsets - same offsets for all etfs */
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#define mmETF_RSZ_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_RSZ - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_STS_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_STS - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_RRD_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_RRD - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_RRP_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_RRP - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_RWP_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_RWP - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_TRG_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_TRG - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_CTL_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_CTL - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_RWD_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_RWD - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_MODE_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_MODE - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_LBUFLEVEL_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_LBUFLEVEL - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_CBUFLEVEL_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_CBUFLEVEL - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_BUFWM_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_BUFWM - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_FFSR_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_FFSR - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_FFCR_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_FFCR - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_PSCR_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_PSCR - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_ITATBMDATA0_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_ITATBMDATA0 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_ITATBMCTR2_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_ITATBMCTR2 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_ITATBMCTR1_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_ITATBMCTR1 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_ITATBMCTR0_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_ITATBMCTR0 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_ITMISCOP0_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_ITMISCOP0 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_ITTRFLIN_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_ITTRFLIN - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_ITATBDATA0_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_ITATBDATA0 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_ITATBCTR2_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_ITATBCTR2 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_ITATBCTR1_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_ITATBCTR1 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_ITATBCTR0_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_ITATBCTR0 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_ITCTRL_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_ITCTRL - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_CLAIMSET_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_CLAIMSET - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_CLAIMCLR_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_CLAIMCLR - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_LAR_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_LAR - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_LSR_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_LSR - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_AUTHSTATUS_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_AUTHSTATUS - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_DEVID_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_DEVID - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_DEVTYPE_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_DEVTYPE - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_PERIPHID4_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_PERIPHID4 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_PERIPHID5_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_PERIPHID5 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_PERIPHID6_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_PERIPHID6 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_PERIPHID7_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_PERIPHID7 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_PERIPHID0_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_PERIPHID0 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_PERIPHID1_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_PERIPHID1 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_PERIPHID2_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_PERIPHID2 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_PERIPHID3_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_PERIPHID3 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_COMPID0_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_COMPID0 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_COMPID1_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_COMPID1 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_COMPID2_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_COMPID2 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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#define mmETF_COMPID3_OFFSET \
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(mmDCORE0_TPC0_EML_ETF_COMPID3 - \
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mmDCORE0_TPC0_EML_ETF_BASE)
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/* STM OFFSETS - same offsets for all stms */
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#define mmSTM_STMDMASTARTR_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMDMASTARTR - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMDMASTOPR_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMDMASTOPR - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMDMASTATR_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMDMASTATR - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMDMACTLR_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMDMACTLR - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMDMAIDR_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMDMAIDR - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMHEER_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMHEER - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMHETER_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMHETER - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMHEBSR_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMHEBSR - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMHEMCR_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMHEMCR - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMHEEXTMUXR_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMHEMASTR_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMHEMASTR - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMHEFEAT1R_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMHEFEAT1R - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMHEIDR_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMHEIDR - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMSPER_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMSPER - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMSPTER_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMSPTER - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMSPSCR_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMSPSCR - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMSPMSCR_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMSPMSCR - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMSPOVERRIDER_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMSPOVERRIDER - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMSPMOVERRIDER_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMSPMOVERRIDER - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMSPTRIGCSR_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMSPTRIGCSR - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMTCSR_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMTCSR - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMTSSTIMR_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMTSSTIMR - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMTSFREQR_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMTSFREQR - \
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mmDCORE0_TPC0_EML_STM_BASE)
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#define mmSTM_STMSYNCR_OFFSET \
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(mmDCORE0_TPC0_EML_STM_STMSYNCR - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMAUXCR_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMAUXCR - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMFEAT1R_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMFEAT1R - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMFEAT2R_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMFEAT2R - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMFEAT3R_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMFEAT3R - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMITTRIGGER_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMITTRIGGER - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMITATBDATA0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMITATBDATA0 - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMITATBCTR2_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMITATBCTR2 - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMITATBID_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMITATBID - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMITATBCTR0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMITATBCTR0 - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMITCTRL_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMITCTRL - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMCLAIMSET_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMCLAIMSET - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMCLAIMCLR_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMCLAIMCLR - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMLAR_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMLAR - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMLSR_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMLSR - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMAUTHSTATUS_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMAUTHSTATUS - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMDEVARCH_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMDEVARCH - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMDEVID_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMDEVID - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMDEVTYPE_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMDEVTYPE - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMPIDR4_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMPIDR4 - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMPIDR5_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMPIDR5 - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMPIDR6_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMPIDR6 - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMPIDR7_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMPIDR7 - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMPIDR0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMPIDR0 - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMPIDR1_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMPIDR1 - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMPIDR2_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMPIDR2 - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMPIDR3_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMPIDR3 - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMCIDR0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMCIDR0 - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMCIDR1_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMCIDR1 - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMCIDR2_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMCIDR2 - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
#define mmSTM_STMCIDR3_OFFSET \
|
|
(mmDCORE0_TPC0_EML_STM_STMCIDR3 - \
|
|
mmDCORE0_TPC0_EML_STM_BASE)
|
|
|
|
|
|
/* SPMU OFFSETS - same offsets for all SPMUs */
|
|
#define mmSPMU_PMEVCNTR0_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMEVCNTR1_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMEVCNTR2_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMEVCNTR3_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMEVCNTR4_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMEVCNTR5_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMCCNTR_L_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMCCNTR_H_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMTRC_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMTRC - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_TRC_CTRL_HOST_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_TRC_STAT_HOST_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_TRC_STAT_HOST - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_TRC_EN_HOST_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_TRC_EN_HOST - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMEVTYPER0_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER0_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMEVTYPER1_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER1_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMEVTYPER2_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER2_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMEVTYPER3_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER3_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMEVTYPER4_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER4_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMEVTYPER5_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER5_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMSSR_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMSSR - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMOVSSR_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMOVSSR - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMCCNTSR_L_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_L - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMCCNTSR_H_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_H - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMEVCNTSR0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMEVCNTSR1_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR1 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMEVCNTSR2_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR2 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMEVCNTSR3_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR3 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMEVCNTSR4_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR4 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMEVCNTSR5_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR5 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMSCR_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMSCR - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMSRR_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMSRR - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMCNTENSET_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMCNTENSET_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMCNTENCLR_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMCNTENCLR_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMINTENSET_EL1_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMINTENSET_EL1 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMINTENCLR_EL1_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMINTENCLR_EL1 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMOVSCLR_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMOVSCLR_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMSWINC_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMSWINC_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMOVSSET_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMOVSSET_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMCFGR_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMCFGR - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMCR_EL0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMCR_EL0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMITCTRL_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMITCTRL - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMCLAIMSET_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMCLAIMSET - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMCLAIMCLR_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMCLAIMCLR - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMDEVAFF0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMDEVAFF0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMDEVAFF1_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMDEVAFF1 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMLAR_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMLAR - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMLSR_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMLSR - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMAUTHSTATUS_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMAUTHSTATUS - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMDEVARCH_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMDEVARCH - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMDEVID2_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMDEVID2 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMDEVID1_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMDEVID1 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMDEVID_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMDEVID - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMDEVTYPE_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMDEVTYPE - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMPIDR4_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMPIDR4 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMPIDR5_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMPIDR5 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMPIDR6_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMPIDR6 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMPIDR7_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMPIDR7 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMPIDR0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMPIDR0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMPIDR1_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMPIDR1 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMPIDR2_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMPIDR2 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMPIDR3_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMPIDR3 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMCIDR0_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMCIDR0 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMCIDR1_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMCIDR1 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMCIDR2_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMCIDR2 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
#define mmSPMU_PMCIDR3_OFFSET \
|
|
(mmDCORE0_TPC0_EML_SPMU_PMCIDR3 - \
|
|
mmDCORE0_TPC0_EML_SPMU_BASE)
|
|
|
|
|
|
/* BMON OFFSETS - same offsets for all BMONs*/
|
|
#define mmBMON_CR_OFFSET \
|
|
(mmDCORE0_TPC0_EML_BUSMON_0_CR - \
|
|
mmDCORE0_TPC0_EML_BUSMON_0_BASE)
|
|
|
|
#define mmBMON_RESET_OFFSET \
|
|
(mmDCORE0_TPC0_EML_BUSMON_0_REG_RESET - \
|
|
mmDCORE0_TPC0_EML_BUSMON_0_BASE)
|
|
|
|
#define mmBMON_INT_CLR_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_INT_CLR - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_TRIG_TH_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_TRIG_TH - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRL_S0_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S0 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRH_S0_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S0 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRL_E0_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E0 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRH_E0_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E0 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRL_S1_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S1 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRH_S1_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S1 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRL_E1_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E1 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRH_E1_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E1 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRL_S2_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S2 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRH_S2_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S2 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRL_E2_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E2 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRH_E2_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E2 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRL_S3_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S3 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRH_S3_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S3 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRL_E3_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E3 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRH_E3_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E3 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_REDUCTION_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_REDUCTION - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_IDL_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_IDL - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_IDH_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_IDH - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_IDENL_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_IDENL - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_IDENH_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_IDENH - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_LATENCY_SMP_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_LATENCY_SMP - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ATTR_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ATTR - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ATTREN_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ATTREN - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_USRENL_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_USRENL - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_USRL_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_USRL - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_USRENH_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_USRENH - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_USRH_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_USRH - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_CAPTURE_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_CAPTURE - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_RELEASE_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_RELEASE - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_WIN_CAPTURE_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_WIN_CAPTURE - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_BW_WIN_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_BW_WIN - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_MATCH_CNT_SOD_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_SOD - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_MATCH_CNT_WIN_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_WIN - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_CYCCNT_L_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_L - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_CYCCNT_H_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_H - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_MAXLAT_SOD_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_MAXLAT_SOD - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_MINLAT_SOD_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_MINLAT_SOD - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_MAXBW_SOD_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_MAXBW_SOD - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_MINBW_SOD_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_MINBW_SOD - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_MAXOS_SOD_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_MAXOS_SOD - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_MINOS_SOD_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_MINOS_SOD - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRL_SNAPSHOT_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_SNAPSHOT - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ADDRH_SNAPSHOT_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_SNAPSHOT - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_IDL_SNAPSHOT_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_IDL_SNAPSHOT - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_IDH_SNAPSHOT_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_IDH_SNAPSHOT - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_ATTR_SNAPSHOT_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_ATTR_SNAPSHOT - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_STM_TRC_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_STM_TRC_DROP_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC_DROP - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_DEVARCH_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_DEVARCH - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_PMDEVID2_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID2 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_PMDEVID1_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID1 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_PMDEVID_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_DEVTYPE_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_DEVTYPE - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_PIDR4_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_PIDR4 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_PIDR5_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_PIDR5 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_PIDR6_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_PIDR6 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_PIDR7_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_PIDR7 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_PIDR0_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_PIDR0 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_PIDR1_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_PIDR1 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_PIDR2_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_PIDR2 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_PIDR3_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_PIDR3 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_CIDR0_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_CIDR0 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_CIDR1_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_CIDR1 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_CIDR2_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_CIDR2 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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#define mmBMON_CIDR3_OFFSET \
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(mmDCORE0_TPC0_EML_BUSMON_0_CIDR3 - \
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mmDCORE0_TPC0_EML_BUSMON_0_BASE)
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/* Coresight unlock offset */
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#define mmCORESIGHT_UNLOCK_REGISTER_OFFSET mmSTM_STMLAR_OFFSET
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#define mmCORESIGHT_UNLOCK_STATUS_REGISTER_OFFSET mmSTM_STMLSR_OFFSET
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#endif /* GAUDI2_CORESIGHT_REGS_DRV_H_ */
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