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![Chunfeng Yun](/assets/img/avatar_default.png)
Add a new OF device ID for mt2701 Some register settings to avoid RX sensitivity level degradation which may arise on mt8173 platform are separated from other platforms. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
635 lines
18 KiB
C
635 lines
18 KiB
C
/*
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* Copyright (c) 2015 MediaTek Inc.
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* Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <dt-bindings/phy/phy.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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/*
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* for sifslv2 register, but exclude port's;
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* relative to USB3_SIF2_BASE base address
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*/
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#define SSUSB_SIFSLV_SPLLC 0x0000
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#define SSUSB_SIFSLV_U2FREQ 0x0100
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/* offsets of sub-segment in each port registers */
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#define SSUSB_SIFSLV_U2PHY_COM_BASE 0x0000
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#define SSUSB_SIFSLV_U3PHYD_BASE 0x0100
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#define SSUSB_USB30_PHYA_SIV_B_BASE 0x0300
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#define SSUSB_SIFSLV_U3PHYA_DA_BASE 0x0400
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#define U3P_USBPHYACR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0000)
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#define PA0_RG_U2PLL_FORCE_ON BIT(15)
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#define U3P_USBPHYACR2 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0008)
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#define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18)
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#define U3P_USBPHYACR5 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0014)
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#define PA5_RG_U2_HSTX_SRCAL_EN BIT(15)
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#define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12)
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#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
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#define PA5_RG_U2_HS_100U_U3_EN BIT(11)
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#define U3P_USBPHYACR6 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0018)
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#define PA6_RG_U2_ISO_EN BIT(31)
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#define PA6_RG_U2_BC11_SW_EN BIT(23)
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#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
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#define PA6_RG_U2_SQTH GENMASK(3, 0)
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#define PA6_RG_U2_SQTH_VAL(x) (0xf & (x))
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#define U3P_U2PHYACR4 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0020)
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#define P2C_RG_USB20_GPIO_CTL BIT(9)
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#define P2C_USB20_GPIO_MODE BIT(8)
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#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
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#define U3D_U2PHYDCR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0060)
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#define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24)
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#define U3P_U2PHYDTM0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0068)
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#define P2C_FORCE_UART_EN BIT(26)
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#define P2C_FORCE_DATAIN BIT(23)
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#define P2C_FORCE_DM_PULLDOWN BIT(21)
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#define P2C_FORCE_DP_PULLDOWN BIT(20)
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#define P2C_FORCE_XCVRSEL BIT(19)
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#define P2C_FORCE_SUSPENDM BIT(18)
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#define P2C_FORCE_TERMSEL BIT(17)
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#define P2C_RG_DATAIN GENMASK(13, 10)
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#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)
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#define P2C_RG_DMPULLDOWN BIT(7)
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#define P2C_RG_DPPULLDOWN BIT(6)
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#define P2C_RG_XCVRSEL GENMASK(5, 4)
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#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)
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#define P2C_RG_SUSPENDM BIT(3)
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#define P2C_RG_TERMSEL BIT(2)
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#define P2C_DTM0_PART_MASK \
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(P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
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P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
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P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
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P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
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#define U3P_U2PHYDTM1 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x006C)
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#define P2C_RG_UART_EN BIT(16)
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#define P2C_RG_VBUSVALID BIT(5)
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#define P2C_RG_SESSEND BIT(4)
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#define P2C_RG_AVALID BIT(2)
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#define U3P_U3_PHYA_REG0 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0000)
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#define P3A_RG_U3_VUSB10_ON BIT(5)
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#define U3P_U3_PHYA_REG6 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0018)
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#define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
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#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
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#define U3P_U3_PHYA_REG9 (SSUSB_USB30_PHYA_SIV_B_BASE + 0x0024)
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#define P3A_RG_RX_DAC_MUX GENMASK(5, 1)
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#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
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#define U3P_U3PHYA_DA_REG0 (SSUSB_SIFSLV_U3PHYA_DA_BASE + 0x0000)
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#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
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#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
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#define U3P_PHYD_CDR1 (SSUSB_SIFSLV_U3PHYD_BASE + 0x005c)
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#define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24)
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#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
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#define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8)
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#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
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#define U3P_XTALCTL3 (SSUSB_SIFSLV_SPLLC + 0x0018)
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#define XC3_RG_U3_XTAL_RX_PWD BIT(9)
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#define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
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#define U3P_U2FREQ_FMCR0 (SSUSB_SIFSLV_U2FREQ + 0x00)
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#define P2F_RG_MONCLK_SEL GENMASK(27, 26)
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#define P2F_RG_MONCLK_SEL_VAL(x) ((0x3 & (x)) << 26)
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#define P2F_RG_FREQDET_EN BIT(24)
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#define P2F_RG_CYCLECNT GENMASK(23, 0)
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#define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x))
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#define U3P_U2FREQ_VALUE (SSUSB_SIFSLV_U2FREQ + 0x0c)
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#define U3P_U2FREQ_FMMONR1 (SSUSB_SIFSLV_U2FREQ + 0x10)
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#define P2F_USB_FM_VALID BIT(0)
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#define P2F_RG_FRCK_EN BIT(8)
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#define U3P_REF_CLK 26 /* MHZ */
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#define U3P_SLEW_RATE_COEF 28
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#define U3P_SR_COEF_DIVISOR 1000
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#define U3P_FM_DET_CYCLE_CNT 1024
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struct mt65xx_phy_pdata {
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/* avoid RX sensitivity level degradation only for mt8173 */
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bool avoid_rx_sen_degradation;
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};
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struct mt65xx_phy_instance {
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struct phy *phy;
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void __iomem *port_base;
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u32 index;
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u8 type;
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};
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struct mt65xx_u3phy {
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struct device *dev;
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void __iomem *sif_base; /* include sif2, but exclude port's */
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struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */
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const struct mt65xx_phy_pdata *pdata;
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struct mt65xx_phy_instance **phys;
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int nphys;
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};
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static void hs_slew_rate_calibrate(struct mt65xx_u3phy *u3phy,
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struct mt65xx_phy_instance *instance)
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{
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void __iomem *sif_base = u3phy->sif_base;
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int calibration_val;
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int fm_out;
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u32 tmp;
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/* enable USB ring oscillator */
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tmp = readl(instance->port_base + U3P_USBPHYACR5);
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tmp |= PA5_RG_U2_HSTX_SRCAL_EN;
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writel(tmp, instance->port_base + U3P_USBPHYACR5);
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udelay(1);
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/*enable free run clock */
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tmp = readl(sif_base + U3P_U2FREQ_FMMONR1);
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tmp |= P2F_RG_FRCK_EN;
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writel(tmp, sif_base + U3P_U2FREQ_FMMONR1);
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/* set cycle count as 1024, and select u2 channel */
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tmp = readl(sif_base + U3P_U2FREQ_FMCR0);
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tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL);
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tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT);
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tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index);
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writel(tmp, sif_base + U3P_U2FREQ_FMCR0);
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/* enable frequency meter */
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tmp = readl(sif_base + U3P_U2FREQ_FMCR0);
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tmp |= P2F_RG_FREQDET_EN;
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writel(tmp, sif_base + U3P_U2FREQ_FMCR0);
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/* ignore return value */
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readl_poll_timeout(sif_base + U3P_U2FREQ_FMMONR1, tmp,
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(tmp & P2F_USB_FM_VALID), 10, 200);
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fm_out = readl(sif_base + U3P_U2FREQ_VALUE);
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/* disable frequency meter */
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tmp = readl(sif_base + U3P_U2FREQ_FMCR0);
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tmp &= ~P2F_RG_FREQDET_EN;
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writel(tmp, sif_base + U3P_U2FREQ_FMCR0);
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/*disable free run clock */
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tmp = readl(sif_base + U3P_U2FREQ_FMMONR1);
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tmp &= ~P2F_RG_FRCK_EN;
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writel(tmp, sif_base + U3P_U2FREQ_FMMONR1);
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if (fm_out) {
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/* ( 1024 / FM_OUT ) x reference clock frequency x 0.028 */
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tmp = U3P_FM_DET_CYCLE_CNT * U3P_REF_CLK * U3P_SLEW_RATE_COEF;
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tmp /= fm_out;
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calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR);
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} else {
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/* if FM detection fail, set default value */
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calibration_val = 4;
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}
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dev_dbg(u3phy->dev, "phy:%d, fm_out:%d, calib:%d\n",
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instance->index, fm_out, calibration_val);
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/* set HS slew rate */
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tmp = readl(instance->port_base + U3P_USBPHYACR5);
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tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
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tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val);
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writel(tmp, instance->port_base + U3P_USBPHYACR5);
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/* disable USB ring oscillator */
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tmp = readl(instance->port_base + U3P_USBPHYACR5);
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tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN;
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writel(tmp, instance->port_base + U3P_USBPHYACR5);
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}
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static void phy_instance_init(struct mt65xx_u3phy *u3phy,
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struct mt65xx_phy_instance *instance)
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{
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void __iomem *port_base = instance->port_base;
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u32 index = instance->index;
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u32 tmp;
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/* switch to USB function. (system register, force ip into usb mode) */
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tmp = readl(port_base + U3P_U2PHYDTM0);
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tmp &= ~P2C_FORCE_UART_EN;
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tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0);
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writel(tmp, port_base + U3P_U2PHYDTM0);
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tmp = readl(port_base + U3P_U2PHYDTM1);
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tmp &= ~P2C_RG_UART_EN;
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writel(tmp, port_base + U3P_U2PHYDTM1);
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if (!index) {
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tmp = readl(port_base + U3P_U2PHYACR4);
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tmp &= ~P2C_U2_GPIO_CTR_MSK;
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writel(tmp, port_base + U3P_U2PHYACR4);
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}
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if (u3phy->pdata->avoid_rx_sen_degradation) {
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if (!index) {
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tmp = readl(port_base + U3P_USBPHYACR2);
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tmp |= PA2_RG_SIF_U2PLL_FORCE_EN;
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writel(tmp, port_base + U3P_USBPHYACR2);
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tmp = readl(port_base + U3D_U2PHYDCR0);
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tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
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writel(tmp, port_base + U3D_U2PHYDCR0);
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} else {
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tmp = readl(port_base + U3D_U2PHYDCR0);
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tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
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writel(tmp, port_base + U3D_U2PHYDCR0);
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tmp = readl(port_base + U3P_U2PHYDTM0);
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tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
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writel(tmp, port_base + U3P_U2PHYDTM0);
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}
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}
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tmp = readl(port_base + U3P_USBPHYACR6);
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tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */
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tmp &= ~PA6_RG_U2_SQTH;
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tmp |= PA6_RG_U2_SQTH_VAL(2);
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writel(tmp, port_base + U3P_USBPHYACR6);
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tmp = readl(port_base + U3P_U3PHYA_DA_REG0);
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tmp &= ~P3A_RG_XTAL_EXT_EN_U3;
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tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2);
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writel(tmp, port_base + U3P_U3PHYA_DA_REG0);
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tmp = readl(port_base + U3P_U3_PHYA_REG9);
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tmp &= ~P3A_RG_RX_DAC_MUX;
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tmp |= P3A_RG_RX_DAC_MUX_VAL(4);
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writel(tmp, port_base + U3P_U3_PHYA_REG9);
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tmp = readl(port_base + U3P_U3_PHYA_REG6);
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tmp &= ~P3A_RG_TX_EIDLE_CM;
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tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe);
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writel(tmp, port_base + U3P_U3_PHYA_REG6);
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tmp = readl(port_base + U3P_PHYD_CDR1);
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tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1);
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tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
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writel(tmp, port_base + U3P_PHYD_CDR1);
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dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
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}
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static void phy_instance_power_on(struct mt65xx_u3phy *u3phy,
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struct mt65xx_phy_instance *instance)
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{
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void __iomem *port_base = instance->port_base;
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u32 index = instance->index;
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u32 tmp;
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if (!index) {
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/* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */
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tmp = readl(port_base + U3P_U3_PHYA_REG0);
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tmp |= P3A_RG_U3_VUSB10_ON;
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writel(tmp, port_base + U3P_U3_PHYA_REG0);
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}
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/* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */
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tmp = readl(port_base + U3P_U2PHYDTM0);
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tmp &= ~(P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL);
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tmp &= ~(P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
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writel(tmp, port_base + U3P_U2PHYDTM0);
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/* OTG Enable */
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tmp = readl(port_base + U3P_USBPHYACR6);
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tmp |= PA6_RG_U2_OTG_VBUSCMP_EN;
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writel(tmp, port_base + U3P_USBPHYACR6);
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if (!index) {
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tmp = readl(u3phy->sif_base + U3P_XTALCTL3);
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tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD;
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writel(tmp, u3phy->sif_base + U3P_XTALCTL3);
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/* switch 100uA current to SSUSB */
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tmp = readl(port_base + U3P_USBPHYACR5);
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tmp |= PA5_RG_U2_HS_100U_U3_EN;
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writel(tmp, port_base + U3P_USBPHYACR5);
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}
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tmp = readl(port_base + U3P_U2PHYDTM1);
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tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID;
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tmp &= ~P2C_RG_SESSEND;
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writel(tmp, port_base + U3P_U2PHYDTM1);
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/* USB 2.0 slew rate calibration */
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tmp = readl(port_base + U3P_USBPHYACR5);
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tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
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tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(4);
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writel(tmp, port_base + U3P_USBPHYACR5);
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if (u3phy->pdata->avoid_rx_sen_degradation && index) {
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tmp = readl(port_base + U3D_U2PHYDCR0);
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tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
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writel(tmp, port_base + U3D_U2PHYDCR0);
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tmp = readl(port_base + U3P_U2PHYDTM0);
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tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
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writel(tmp, port_base + U3P_U2PHYDTM0);
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}
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dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
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}
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static void phy_instance_power_off(struct mt65xx_u3phy *u3phy,
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struct mt65xx_phy_instance *instance)
|
|
{
|
|
void __iomem *port_base = instance->port_base;
|
|
u32 index = instance->index;
|
|
u32 tmp;
|
|
|
|
tmp = readl(port_base + U3P_U2PHYDTM0);
|
|
tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN);
|
|
tmp |= P2C_FORCE_SUSPENDM;
|
|
writel(tmp, port_base + U3P_U2PHYDTM0);
|
|
|
|
/* OTG Disable */
|
|
tmp = readl(port_base + U3P_USBPHYACR6);
|
|
tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN;
|
|
writel(tmp, port_base + U3P_USBPHYACR6);
|
|
|
|
if (!index) {
|
|
/* switch 100uA current back to USB2.0 */
|
|
tmp = readl(port_base + U3P_USBPHYACR5);
|
|
tmp &= ~PA5_RG_U2_HS_100U_U3_EN;
|
|
writel(tmp, port_base + U3P_USBPHYACR5);
|
|
}
|
|
|
|
/* let suspendm=0, set utmi into analog power down */
|
|
tmp = readl(port_base + U3P_U2PHYDTM0);
|
|
tmp &= ~P2C_RG_SUSPENDM;
|
|
writel(tmp, port_base + U3P_U2PHYDTM0);
|
|
udelay(1);
|
|
|
|
tmp = readl(port_base + U3P_U2PHYDTM1);
|
|
tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID);
|
|
tmp |= P2C_RG_SESSEND;
|
|
writel(tmp, port_base + U3P_U2PHYDTM1);
|
|
|
|
if (!index) {
|
|
tmp = readl(port_base + U3P_U3_PHYA_REG0);
|
|
tmp &= ~P3A_RG_U3_VUSB10_ON;
|
|
writel(tmp, port_base + U3P_U3_PHYA_REG0);
|
|
}
|
|
|
|
if (u3phy->pdata->avoid_rx_sen_degradation && index) {
|
|
tmp = readl(port_base + U3D_U2PHYDCR0);
|
|
tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
|
|
writel(tmp, port_base + U3D_U2PHYDCR0);
|
|
}
|
|
|
|
dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
|
|
}
|
|
|
|
static void phy_instance_exit(struct mt65xx_u3phy *u3phy,
|
|
struct mt65xx_phy_instance *instance)
|
|
{
|
|
void __iomem *port_base = instance->port_base;
|
|
u32 index = instance->index;
|
|
u32 tmp;
|
|
|
|
if (u3phy->pdata->avoid_rx_sen_degradation && index) {
|
|
tmp = readl(port_base + U3D_U2PHYDCR0);
|
|
tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
|
|
writel(tmp, port_base + U3D_U2PHYDCR0);
|
|
|
|
tmp = readl(port_base + U3P_U2PHYDTM0);
|
|
tmp &= ~P2C_FORCE_SUSPENDM;
|
|
writel(tmp, port_base + U3P_U2PHYDTM0);
|
|
}
|
|
}
|
|
|
|
static int mt65xx_phy_init(struct phy *phy)
|
|
{
|
|
struct mt65xx_phy_instance *instance = phy_get_drvdata(phy);
|
|
struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(u3phy->u3phya_ref);
|
|
if (ret) {
|
|
dev_err(u3phy->dev, "failed to enable u3phya_ref\n");
|
|
return ret;
|
|
}
|
|
|
|
phy_instance_init(u3phy, instance);
|
|
return 0;
|
|
}
|
|
|
|
static int mt65xx_phy_power_on(struct phy *phy)
|
|
{
|
|
struct mt65xx_phy_instance *instance = phy_get_drvdata(phy);
|
|
struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
|
|
|
|
phy_instance_power_on(u3phy, instance);
|
|
hs_slew_rate_calibrate(u3phy, instance);
|
|
return 0;
|
|
}
|
|
|
|
static int mt65xx_phy_power_off(struct phy *phy)
|
|
{
|
|
struct mt65xx_phy_instance *instance = phy_get_drvdata(phy);
|
|
struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
|
|
|
|
phy_instance_power_off(u3phy, instance);
|
|
return 0;
|
|
}
|
|
|
|
static int mt65xx_phy_exit(struct phy *phy)
|
|
{
|
|
struct mt65xx_phy_instance *instance = phy_get_drvdata(phy);
|
|
struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
|
|
|
|
phy_instance_exit(u3phy, instance);
|
|
clk_disable_unprepare(u3phy->u3phya_ref);
|
|
return 0;
|
|
}
|
|
|
|
static struct phy *mt65xx_phy_xlate(struct device *dev,
|
|
struct of_phandle_args *args)
|
|
{
|
|
struct mt65xx_u3phy *u3phy = dev_get_drvdata(dev);
|
|
struct mt65xx_phy_instance *instance = NULL;
|
|
struct device_node *phy_np = args->np;
|
|
int index;
|
|
|
|
|
|
if (args->args_count != 1) {
|
|
dev_err(dev, "invalid number of cells in 'phy' property\n");
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
for (index = 0; index < u3phy->nphys; index++)
|
|
if (phy_np == u3phy->phys[index]->phy->dev.of_node) {
|
|
instance = u3phy->phys[index];
|
|
break;
|
|
}
|
|
|
|
if (!instance) {
|
|
dev_err(dev, "failed to find appropriate phy\n");
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
instance->type = args->args[0];
|
|
|
|
if (!(instance->type == PHY_TYPE_USB2 ||
|
|
instance->type == PHY_TYPE_USB3)) {
|
|
dev_err(dev, "unsupported device type: %d\n", instance->type);
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
return instance->phy;
|
|
}
|
|
|
|
static struct phy_ops mt65xx_u3phy_ops = {
|
|
.init = mt65xx_phy_init,
|
|
.exit = mt65xx_phy_exit,
|
|
.power_on = mt65xx_phy_power_on,
|
|
.power_off = mt65xx_phy_power_off,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static const struct mt65xx_phy_pdata mt2701_pdata = {
|
|
.avoid_rx_sen_degradation = false,
|
|
};
|
|
|
|
static const struct mt65xx_phy_pdata mt8173_pdata = {
|
|
.avoid_rx_sen_degradation = true,
|
|
};
|
|
|
|
static const struct of_device_id mt65xx_u3phy_id_table[] = {
|
|
{ .compatible = "mediatek,mt2701-u3phy", .data = &mt2701_pdata },
|
|
{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mt65xx_u3phy_id_table);
|
|
|
|
static int mt65xx_u3phy_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *match;
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
struct device_node *child_np;
|
|
struct phy_provider *provider;
|
|
struct resource *sif_res;
|
|
struct mt65xx_u3phy *u3phy;
|
|
struct resource res;
|
|
int port, retval;
|
|
|
|
match = of_match_node(mt65xx_u3phy_id_table, pdev->dev.of_node);
|
|
if (!match)
|
|
return -EINVAL;
|
|
|
|
u3phy = devm_kzalloc(dev, sizeof(*u3phy), GFP_KERNEL);
|
|
if (!u3phy)
|
|
return -ENOMEM;
|
|
|
|
u3phy->pdata = match->data;
|
|
u3phy->nphys = of_get_child_count(np);
|
|
u3phy->phys = devm_kcalloc(dev, u3phy->nphys,
|
|
sizeof(*u3phy->phys), GFP_KERNEL);
|
|
if (!u3phy->phys)
|
|
return -ENOMEM;
|
|
|
|
u3phy->dev = dev;
|
|
platform_set_drvdata(pdev, u3phy);
|
|
|
|
sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
u3phy->sif_base = devm_ioremap_resource(dev, sif_res);
|
|
if (IS_ERR(u3phy->sif_base)) {
|
|
dev_err(dev, "failed to remap sif regs\n");
|
|
return PTR_ERR(u3phy->sif_base);
|
|
}
|
|
|
|
u3phy->u3phya_ref = devm_clk_get(dev, "u3phya_ref");
|
|
if (IS_ERR(u3phy->u3phya_ref)) {
|
|
dev_err(dev, "error to get u3phya_ref\n");
|
|
return PTR_ERR(u3phy->u3phya_ref);
|
|
}
|
|
|
|
port = 0;
|
|
for_each_child_of_node(np, child_np) {
|
|
struct mt65xx_phy_instance *instance;
|
|
struct phy *phy;
|
|
|
|
instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
|
|
if (!instance) {
|
|
retval = -ENOMEM;
|
|
goto put_child;
|
|
}
|
|
|
|
u3phy->phys[port] = instance;
|
|
|
|
phy = devm_phy_create(dev, child_np, &mt65xx_u3phy_ops);
|
|
if (IS_ERR(phy)) {
|
|
dev_err(dev, "failed to create phy\n");
|
|
retval = PTR_ERR(phy);
|
|
goto put_child;
|
|
}
|
|
|
|
retval = of_address_to_resource(child_np, 0, &res);
|
|
if (retval) {
|
|
dev_err(dev, "failed to get address resource(id-%d)\n",
|
|
port);
|
|
goto put_child;
|
|
}
|
|
|
|
instance->port_base = devm_ioremap_resource(&phy->dev, &res);
|
|
if (IS_ERR(instance->port_base)) {
|
|
dev_err(dev, "failed to remap phy regs\n");
|
|
retval = PTR_ERR(instance->port_base);
|
|
goto put_child;
|
|
}
|
|
|
|
instance->phy = phy;
|
|
instance->index = port;
|
|
phy_set_drvdata(phy, instance);
|
|
port++;
|
|
}
|
|
|
|
provider = devm_of_phy_provider_register(dev, mt65xx_phy_xlate);
|
|
|
|
return PTR_ERR_OR_ZERO(provider);
|
|
put_child:
|
|
of_node_put(child_np);
|
|
return retval;
|
|
}
|
|
|
|
static struct platform_driver mt65xx_u3phy_driver = {
|
|
.probe = mt65xx_u3phy_probe,
|
|
.driver = {
|
|
.name = "mt65xx-u3phy",
|
|
.of_match_table = mt65xx_u3phy_id_table,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(mt65xx_u3phy_driver);
|
|
|
|
MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
|
|
MODULE_DESCRIPTION("mt65xx USB PHY driver");
|
|
MODULE_LICENSE("GPL v2");
|