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![Seungwon Jeon](/assets/img/avatar_default.png)
Add checking whether the clock is valid. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
518 lines
14 KiB
C
518 lines
14 KiB
C
/*
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* Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
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*
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* Copyright (C) 2012, Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/dw_mmc.h>
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#include <linux/mmc/mmc.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/slab.h>
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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#define NUM_PINS(x) (x + 2)
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#define SDMMC_CLKSEL 0x09C
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#define SDMMC_CLKSEL64 0x0A8
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#define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0)
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#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
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#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
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#define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7)
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#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \
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SDMMC_CLKSEL_CCLK_DRIVE(y) | \
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SDMMC_CLKSEL_CCLK_DIVIDER(z))
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#define SDMMC_CLKSEL_WAKEUP_INT BIT(11)
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#define EXYNOS4210_FIXED_CIU_CLK_DIV 2
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#define EXYNOS4412_FIXED_CIU_CLK_DIV 4
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/* Block number in eMMC */
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#define DWMCI_BLOCK_NUM 0xFFFFFFFF
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#define SDMMC_EMMCP_BASE 0x1000
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#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010)
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#define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200)
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#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204)
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#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C)
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/* SMU control bits */
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#define DWMCI_MPSCTRL_SECURE_READ_BIT BIT(7)
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#define DWMCI_MPSCTRL_SECURE_WRITE_BIT BIT(6)
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#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT BIT(5)
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#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4)
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#define DWMCI_MPSCTRL_USE_FUSE_KEY BIT(3)
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#define DWMCI_MPSCTRL_ECB_MODE BIT(2)
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#define DWMCI_MPSCTRL_ENCRYPTION BIT(1)
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#define DWMCI_MPSCTRL_VALID BIT(0)
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#define EXYNOS_CCLKIN_MIN 50000000 /* unit: HZ */
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/* Variations in Exynos specific dw-mshc controller */
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enum dw_mci_exynos_type {
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DW_MCI_TYPE_EXYNOS4210,
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DW_MCI_TYPE_EXYNOS4412,
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DW_MCI_TYPE_EXYNOS5250,
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DW_MCI_TYPE_EXYNOS5420,
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DW_MCI_TYPE_EXYNOS5420_SMU,
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DW_MCI_TYPE_EXYNOS7,
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DW_MCI_TYPE_EXYNOS7_SMU,
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};
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/* Exynos implementation specific driver private data */
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struct dw_mci_exynos_priv_data {
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enum dw_mci_exynos_type ctrl_type;
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u8 ciu_div;
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u32 sdr_timing;
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u32 ddr_timing;
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u32 cur_speed;
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};
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static struct dw_mci_exynos_compatible {
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char *compatible;
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enum dw_mci_exynos_type ctrl_type;
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} exynos_compat[] = {
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{
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.compatible = "samsung,exynos4210-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS4210,
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}, {
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.compatible = "samsung,exynos4412-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS4412,
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}, {
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.compatible = "samsung,exynos5250-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS5250,
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}, {
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.compatible = "samsung,exynos5420-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS5420,
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}, {
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.compatible = "samsung,exynos5420-dw-mshc-smu",
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.ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU,
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}, {
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.compatible = "samsung,exynos7-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS7,
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}, {
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.compatible = "samsung,exynos7-dw-mshc-smu",
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.ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU,
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},
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};
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static int dw_mci_exynos_priv_init(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
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mci_writel(host, MPSBEGIN0, 0);
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mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
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mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
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DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
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DWMCI_MPSCTRL_VALID |
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DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
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}
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return 0;
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}
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static int dw_mci_exynos_setup_clock(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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host->bus_hz /= (priv->ciu_div + 1);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int dw_mci_exynos_suspend(struct device *dev)
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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return dw_mci_suspend(host);
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}
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static int dw_mci_exynos_resume(struct device *dev)
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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dw_mci_exynos_priv_init(host);
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return dw_mci_resume(host);
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}
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/**
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* dw_mci_exynos_resume_noirq - Exynos-specific resume code
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*
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* On exynos5420 there is a silicon errata that will sometimes leave the
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* WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate
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* that it fired and we can clear it by writing a 1 back. Clear it to prevent
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* interrupts from going off constantly.
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*
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* We run this code on all exynos variants because it doesn't hurt.
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*/
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static int dw_mci_exynos_resume_noirq(struct device *dev)
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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struct dw_mci_exynos_priv_data *priv = host->priv;
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u32 clksel;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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clksel = mci_readl(host, CLKSEL64);
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else
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clksel = mci_readl(host, CLKSEL);
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if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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mci_writel(host, CLKSEL64, clksel);
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else
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mci_writel(host, CLKSEL, clksel);
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}
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return 0;
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}
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#else
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#define dw_mci_exynos_suspend NULL
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#define dw_mci_exynos_resume NULL
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#define dw_mci_exynos_resume_noirq NULL
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#endif /* CONFIG_PM_SLEEP */
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static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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/*
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* Exynos4412 and Exynos5250 extends the use of CMD register with the
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* use of bit 29 (which is reserved on standard MSHC controllers) for
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* optionally bypassing the HOLD register for command and data. The
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* HOLD register should be bypassed in case there is no phase shift
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* applied on CMD/DATA that is sent to the card.
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*/
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
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if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL64)))
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*cmdr |= SDMMC_CMD_USE_HOLD_REG;
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} else {
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if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
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*cmdr |= SDMMC_CMD_USE_HOLD_REG;
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}
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}
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static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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unsigned int wanted = ios->clock;
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unsigned long actual;
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u8 div = priv->ciu_div + 1;
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if (ios->timing == MMC_TIMING_MMC_DDR52) {
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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mci_writel(host, CLKSEL64, priv->ddr_timing);
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else
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mci_writel(host, CLKSEL, priv->ddr_timing);
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/* Should be double rate for DDR mode */
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if (ios->bus_width == MMC_BUS_WIDTH_8)
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wanted <<= 1;
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} else {
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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mci_writel(host, CLKSEL64, priv->sdr_timing);
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else
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mci_writel(host, CLKSEL, priv->sdr_timing);
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}
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/*
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* Don't care if wanted clock is zero or
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* ciu clock is unavailable
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*/
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if (!wanted || IS_ERR(host->ciu_clk))
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return;
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/* Guaranteed minimum frequency for cclkin */
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if (wanted < EXYNOS_CCLKIN_MIN)
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wanted = EXYNOS_CCLKIN_MIN;
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if (wanted != priv->cur_speed) {
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int ret = clk_set_rate(host->ciu_clk, wanted * div);
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if (ret)
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dev_warn(host->dev,
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"failed to set clk-rate %u error: %d\n",
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wanted * div, ret);
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actual = clk_get_rate(host->ciu_clk);
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host->bus_hz = actual / div;
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priv->cur_speed = wanted;
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host->current_speed = 0;
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}
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}
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static int dw_mci_exynos_parse_dt(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv;
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struct device_node *np = host->dev->of_node;
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u32 timing[2];
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u32 div = 0;
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int idx;
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int ret;
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priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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dev_err(host->dev, "mem alloc failed for private data\n");
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return -ENOMEM;
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}
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for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
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if (of_device_is_compatible(np, exynos_compat[idx].compatible))
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priv->ctrl_type = exynos_compat[idx].ctrl_type;
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}
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
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priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
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priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
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else {
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of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
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priv->ciu_div = div;
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}
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ret = of_property_read_u32_array(np,
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"samsung,dw-mshc-sdr-timing", timing, 2);
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if (ret)
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return ret;
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priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
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ret = of_property_read_u32_array(np,
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"samsung,dw-mshc-ddr-timing", timing, 2);
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if (ret)
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return ret;
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priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
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host->priv = priv;
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return 0;
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}
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static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
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else
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return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
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}
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static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
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{
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u32 clksel;
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struct dw_mci_exynos_priv_data *priv = host->priv;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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clksel = mci_readl(host, CLKSEL64);
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else
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clksel = mci_readl(host, CLKSEL);
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clksel = (clksel & ~0x7) | SDMMC_CLKSEL_CCLK_SAMPLE(sample);
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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mci_writel(host, CLKSEL64, clksel);
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else
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mci_writel(host, CLKSEL, clksel);
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}
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static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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u32 clksel;
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u8 sample;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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clksel = mci_readl(host, CLKSEL64);
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else
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clksel = mci_readl(host, CLKSEL);
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sample = (clksel + 1) & 0x7;
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clksel = (clksel & ~0x7) | sample;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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mci_writel(host, CLKSEL64, clksel);
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else
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mci_writel(host, CLKSEL, clksel);
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return sample;
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}
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static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates)
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{
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const u8 iter = 8;
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u8 __c;
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s8 i, loc = -1;
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for (i = 0; i < iter; i++) {
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__c = ror8(candiates, i);
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if ((__c & 0xc7) == 0xc7) {
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loc = i;
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goto out;
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}
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}
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for (i = 0; i < iter; i++) {
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__c = ror8(candiates, i);
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if ((__c & 0x83) == 0x83) {
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loc = i;
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goto out;
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}
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}
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out:
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return loc;
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}
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static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
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struct dw_mci_tuning_data *tuning_data)
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{
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struct dw_mci *host = slot->host;
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struct mmc_host *mmc = slot->mmc;
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const u8 *blk_pattern = tuning_data->blk_pattern;
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u8 *blk_test;
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unsigned int blksz = tuning_data->blksz;
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u8 start_smpl, smpl, candiates = 0;
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s8 found = -1;
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int ret = 0;
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blk_test = kmalloc(blksz, GFP_KERNEL);
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if (!blk_test)
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return -ENOMEM;
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start_smpl = dw_mci_exynos_get_clksmpl(host);
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do {
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struct mmc_request mrq = {NULL};
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struct mmc_command cmd = {0};
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struct mmc_command stop = {0};
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struct mmc_data data = {0};
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struct scatterlist sg;
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cmd.opcode = opcode;
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cmd.arg = 0;
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cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
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stop.opcode = MMC_STOP_TRANSMISSION;
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stop.arg = 0;
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stop.flags = MMC_RSP_R1B | MMC_CMD_AC;
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data.blksz = blksz;
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data.blocks = 1;
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data.flags = MMC_DATA_READ;
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data.sg = &sg;
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data.sg_len = 1;
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sg_init_one(&sg, blk_test, blksz);
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mrq.cmd = &cmd;
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mrq.stop = &stop;
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mrq.data = &data;
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host->mrq = &mrq;
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mci_writel(host, TMOUT, ~0);
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smpl = dw_mci_exynos_move_next_clksmpl(host);
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mmc_wait_for_req(mmc, &mrq);
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if (!cmd.error && !data.error) {
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if (!memcmp(blk_pattern, blk_test, blksz))
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candiates |= (1 << smpl);
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} else {
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dev_dbg(host->dev,
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"Tuning error: cmd.error:%d, data.error:%d\n",
|
|
cmd.error, data.error);
|
|
}
|
|
} while (start_smpl != smpl);
|
|
|
|
found = dw_mci_exynos_get_best_clksmpl(candiates);
|
|
if (found >= 0)
|
|
dw_mci_exynos_set_clksmpl(host, found);
|
|
else
|
|
ret = -EIO;
|
|
|
|
kfree(blk_test);
|
|
return ret;
|
|
}
|
|
|
|
/* Common capabilities of Exynos4/Exynos5 SoC */
|
|
static unsigned long exynos_dwmmc_caps[4] = {
|
|
MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
|
|
MMC_CAP_CMD23,
|
|
MMC_CAP_CMD23,
|
|
MMC_CAP_CMD23,
|
|
};
|
|
|
|
static const struct dw_mci_drv_data exynos_drv_data = {
|
|
.caps = exynos_dwmmc_caps,
|
|
.init = dw_mci_exynos_priv_init,
|
|
.setup_clock = dw_mci_exynos_setup_clock,
|
|
.prepare_command = dw_mci_exynos_prepare_command,
|
|
.set_ios = dw_mci_exynos_set_ios,
|
|
.parse_dt = dw_mci_exynos_parse_dt,
|
|
.execute_tuning = dw_mci_exynos_execute_tuning,
|
|
};
|
|
|
|
static const struct of_device_id dw_mci_exynos_match[] = {
|
|
{ .compatible = "samsung,exynos4412-dw-mshc",
|
|
.data = &exynos_drv_data, },
|
|
{ .compatible = "samsung,exynos5250-dw-mshc",
|
|
.data = &exynos_drv_data, },
|
|
{ .compatible = "samsung,exynos5420-dw-mshc",
|
|
.data = &exynos_drv_data, },
|
|
{ .compatible = "samsung,exynos5420-dw-mshc-smu",
|
|
.data = &exynos_drv_data, },
|
|
{ .compatible = "samsung,exynos7-dw-mshc",
|
|
.data = &exynos_drv_data, },
|
|
{ .compatible = "samsung,exynos7-dw-mshc-smu",
|
|
.data = &exynos_drv_data, },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
|
|
|
|
static int dw_mci_exynos_probe(struct platform_device *pdev)
|
|
{
|
|
const struct dw_mci_drv_data *drv_data;
|
|
const struct of_device_id *match;
|
|
|
|
match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
|
|
drv_data = match->data;
|
|
return dw_mci_pltfm_register(pdev, drv_data);
|
|
}
|
|
|
|
static const struct dev_pm_ops dw_mci_exynos_pmops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
|
|
.resume_noirq = dw_mci_exynos_resume_noirq,
|
|
.thaw_noirq = dw_mci_exynos_resume_noirq,
|
|
.restore_noirq = dw_mci_exynos_resume_noirq,
|
|
};
|
|
|
|
static struct platform_driver dw_mci_exynos_pltfm_driver = {
|
|
.probe = dw_mci_exynos_probe,
|
|
.remove = __exit_p(dw_mci_pltfm_remove),
|
|
.driver = {
|
|
.name = "dwmmc_exynos",
|
|
.of_match_table = dw_mci_exynos_match,
|
|
.pm = &dw_mci_exynos_pmops,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(dw_mci_exynos_pltfm_driver);
|
|
|
|
MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
|
|
MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:dwmmc-exynos");
|