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![Kyungmin Park](/assets/img/avatar_default.png)
Move the Samsung s5pv210 SoC GPIO driver to drivers/gpio Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
288 lines
5.9 KiB
C
288 lines
5.9 KiB
C
/* linux/arch/arm/mach-s5pv210/gpiolib.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5PV210 - GPIOlib support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <plat/gpio-core.h>
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#include <plat/gpio-cfg.h>
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#include <plat/gpio-cfg-helpers.h>
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#include <mach/map.h>
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static struct s3c_gpio_cfg gpio_cfg = {
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.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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static struct s3c_gpio_cfg gpio_cfg_noint = {
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.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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/* GPIO bank's base address given the index of the bank in the
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* list of all gpio banks.
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*/
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#define S5PV210_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20))
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/*
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* Following are the gpio banks in v210.
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*
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* The 'config' member when left to NULL, is initialized to the default
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* structure gpio_cfg in the init function below.
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*
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* The 'base' member is also initialized in the init function below.
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* Note: The initialization of 'base' member of s3c_gpio_chip structure
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* uses the above macro and depends on the banks being listed in order here.
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*/
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static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
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{
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.chip = {
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.base = S5PV210_GPA0(0),
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.ngpio = S5PV210_GPIO_A0_NR,
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.label = "GPA0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPA1(0),
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.ngpio = S5PV210_GPIO_A1_NR,
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.label = "GPA1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPB(0),
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.ngpio = S5PV210_GPIO_B_NR,
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.label = "GPB",
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},
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}, {
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.chip = {
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.base = S5PV210_GPC0(0),
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.ngpio = S5PV210_GPIO_C0_NR,
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.label = "GPC0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPC1(0),
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.ngpio = S5PV210_GPIO_C1_NR,
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.label = "GPC1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPD0(0),
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.ngpio = S5PV210_GPIO_D0_NR,
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.label = "GPD0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPD1(0),
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.ngpio = S5PV210_GPIO_D1_NR,
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.label = "GPD1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPE0(0),
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.ngpio = S5PV210_GPIO_E0_NR,
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.label = "GPE0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPE1(0),
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.ngpio = S5PV210_GPIO_E1_NR,
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.label = "GPE1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPF0(0),
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.ngpio = S5PV210_GPIO_F0_NR,
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.label = "GPF0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPF1(0),
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.ngpio = S5PV210_GPIO_F1_NR,
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.label = "GPF1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPF2(0),
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.ngpio = S5PV210_GPIO_F2_NR,
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.label = "GPF2",
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},
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}, {
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.chip = {
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.base = S5PV210_GPF3(0),
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.ngpio = S5PV210_GPIO_F3_NR,
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.label = "GPF3",
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},
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}, {
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.chip = {
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.base = S5PV210_GPG0(0),
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.ngpio = S5PV210_GPIO_G0_NR,
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.label = "GPG0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPG1(0),
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.ngpio = S5PV210_GPIO_G1_NR,
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.label = "GPG1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPG2(0),
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.ngpio = S5PV210_GPIO_G2_NR,
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.label = "GPG2",
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},
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}, {
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.chip = {
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.base = S5PV210_GPG3(0),
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.ngpio = S5PV210_GPIO_G3_NR,
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.label = "GPG3",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = S5PV210_GPI(0),
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.ngpio = S5PV210_GPIO_I_NR,
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.label = "GPI",
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},
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}, {
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.chip = {
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.base = S5PV210_GPJ0(0),
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.ngpio = S5PV210_GPIO_J0_NR,
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.label = "GPJ0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPJ1(0),
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.ngpio = S5PV210_GPIO_J1_NR,
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.label = "GPJ1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPJ2(0),
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.ngpio = S5PV210_GPIO_J2_NR,
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.label = "GPJ2",
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},
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}, {
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.chip = {
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.base = S5PV210_GPJ3(0),
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.ngpio = S5PV210_GPIO_J3_NR,
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.label = "GPJ3",
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},
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}, {
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.chip = {
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.base = S5PV210_GPJ4(0),
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.ngpio = S5PV210_GPIO_J4_NR,
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.label = "GPJ4",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = S5PV210_MP01(0),
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.ngpio = S5PV210_GPIO_MP01_NR,
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.label = "MP01",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = S5PV210_MP02(0),
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.ngpio = S5PV210_GPIO_MP02_NR,
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.label = "MP02",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = S5PV210_MP03(0),
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.ngpio = S5PV210_GPIO_MP03_NR,
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.label = "MP03",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = S5PV210_MP04(0),
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.ngpio = S5PV210_GPIO_MP04_NR,
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.label = "MP04",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = S5PV210_MP05(0),
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.ngpio = S5PV210_GPIO_MP05_NR,
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.label = "MP05",
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},
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}, {
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.base = (S5P_VA_GPIO + 0xC00),
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.config = &gpio_cfg_noint,
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.irq_base = IRQ_EINT(0),
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.chip = {
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.base = S5PV210_GPH0(0),
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.ngpio = S5PV210_GPIO_H0_NR,
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.label = "GPH0",
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.to_irq = samsung_gpiolib_to_irq,
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},
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}, {
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.base = (S5P_VA_GPIO + 0xC20),
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.config = &gpio_cfg_noint,
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.irq_base = IRQ_EINT(8),
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.chip = {
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.base = S5PV210_GPH1(0),
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.ngpio = S5PV210_GPIO_H1_NR,
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.label = "GPH1",
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.to_irq = samsung_gpiolib_to_irq,
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},
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}, {
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.base = (S5P_VA_GPIO + 0xC40),
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.config = &gpio_cfg_noint,
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.irq_base = IRQ_EINT(16),
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.chip = {
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.base = S5PV210_GPH2(0),
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.ngpio = S5PV210_GPIO_H2_NR,
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.label = "GPH2",
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.to_irq = samsung_gpiolib_to_irq,
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},
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}, {
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.base = (S5P_VA_GPIO + 0xC60),
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.config = &gpio_cfg_noint,
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.irq_base = IRQ_EINT(24),
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.chip = {
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.base = S5PV210_GPH3(0),
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.ngpio = S5PV210_GPIO_H3_NR,
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.label = "GPH3",
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.to_irq = samsung_gpiolib_to_irq,
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},
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},
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};
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static __init int s5pv210_gpiolib_init(void)
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{
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struct s3c_gpio_chip *chip = s5pv210_gpio_4bit;
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int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit);
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int gpioint_group = 0;
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int i = 0;
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for (i = 0; i < nr_chips; i++, chip++) {
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if (chip->config == NULL) {
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chip->config = &gpio_cfg;
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chip->group = gpioint_group++;
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}
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if (chip->base == NULL)
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chip->base = S5PV210_BANK_BASE(i);
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}
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samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips);
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s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
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return 0;
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}
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core_initcall(s5pv210_gpiolib_init);
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