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![Julia Lawall](/assets/img/avatar_default.png)
Request_mem_region should be used with release_mem_region, not release_resource. The semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @s exists@ expression e1,e2,e3,e4,e; @@ *e4 = request_mem_region(e1,e2,e3) ... when != e4 = e *release_resource(e4); // </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
1142 lines
28 KiB
C
1142 lines
28 KiB
C
/* linux/drivers/video/s3c2410fb.c
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* Copyright (c) 2004,2005 Arnaud Patard
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* Copyright (c) 2004-2008 Ben Dooks
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*
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* S3C2410 LCD Framebuffer Driver
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*
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* Driver based on skeletonfb.c, sa1100fb.c and others.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/fb.h>
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#include <linux/init.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <asm/io.h>
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#include <asm/div64.h>
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#include <asm/mach/map.h>
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#include <mach/regs-lcd.h>
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#include <mach/regs-gpio.h>
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#include <mach/fb.h>
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#ifdef CONFIG_PM
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#include <linux/pm.h>
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#endif
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#include "s3c2410fb.h"
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/* Debugging stuff */
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#ifdef CONFIG_FB_S3C2410_DEBUG
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static int debug = 1;
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#else
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static int debug = 0;
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#endif
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#define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
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/* useful functions */
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static int is_s3c2412(struct s3c2410fb_info *fbi)
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{
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return (fbi->drv_type == DRV_S3C2412);
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}
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/* s3c2410fb_set_lcdaddr
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*
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* initialise lcd controller address pointers
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*/
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static void s3c2410fb_set_lcdaddr(struct fb_info *info)
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{
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unsigned long saddr1, saddr2, saddr3;
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struct s3c2410fb_info *fbi = info->par;
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void __iomem *regs = fbi->io;
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saddr1 = info->fix.smem_start >> 1;
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saddr2 = info->fix.smem_start;
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saddr2 += info->fix.line_length * info->var.yres;
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saddr2 >>= 1;
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saddr3 = S3C2410_OFFSIZE(0) |
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S3C2410_PAGEWIDTH((info->fix.line_length / 2) & 0x3ff);
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dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
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dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
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dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
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writel(saddr1, regs + S3C2410_LCDSADDR1);
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writel(saddr2, regs + S3C2410_LCDSADDR2);
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writel(saddr3, regs + S3C2410_LCDSADDR3);
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}
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/* s3c2410fb_calc_pixclk()
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*
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* calculate divisor for clk->pixclk
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*/
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static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
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unsigned long pixclk)
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{
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unsigned long clk = fbi->clk_rate;
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unsigned long long div;
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/* pixclk is in picoseconds, our clock is in Hz
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*
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* Hz -> picoseconds is / 10^-12
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*/
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div = (unsigned long long)clk * pixclk;
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div >>= 12; /* div / 2^12 */
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do_div(div, 625 * 625UL * 625); /* div / 5^12 */
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dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
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return div;
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}
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/*
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* s3c2410fb_check_var():
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* Get the video params out of 'var'. If a value doesn't fit, round it up,
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* if it's too big, return -EINVAL.
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*
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*/
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static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
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struct fb_info *info)
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{
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struct s3c2410fb_info *fbi = info->par;
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struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
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struct s3c2410fb_display *display = NULL;
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struct s3c2410fb_display *default_display = mach_info->displays +
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mach_info->default_display;
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int type = default_display->type;
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unsigned i;
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dprintk("check_var(var=%p, info=%p)\n", var, info);
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/* validate x/y resolution */
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/* choose default mode if possible */
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if (var->yres == default_display->yres &&
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var->xres == default_display->xres &&
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var->bits_per_pixel == default_display->bpp)
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display = default_display;
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else
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for (i = 0; i < mach_info->num_displays; i++)
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if (type == mach_info->displays[i].type &&
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var->yres == mach_info->displays[i].yres &&
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var->xres == mach_info->displays[i].xres &&
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var->bits_per_pixel == mach_info->displays[i].bpp) {
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display = mach_info->displays + i;
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break;
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}
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if (!display) {
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dprintk("wrong resolution or depth %dx%d at %d bpp\n",
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var->xres, var->yres, var->bits_per_pixel);
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return -EINVAL;
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}
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/* it is always the size as the display */
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var->xres_virtual = display->xres;
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var->yres_virtual = display->yres;
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var->height = display->height;
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var->width = display->width;
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/* copy lcd settings */
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var->pixclock = display->pixclock;
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var->left_margin = display->left_margin;
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var->right_margin = display->right_margin;
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var->upper_margin = display->upper_margin;
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var->lower_margin = display->lower_margin;
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var->vsync_len = display->vsync_len;
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var->hsync_len = display->hsync_len;
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fbi->regs.lcdcon5 = display->lcdcon5;
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/* set display type */
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fbi->regs.lcdcon1 = display->type;
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var->transp.offset = 0;
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var->transp.length = 0;
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/* set r/g/b positions */
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switch (var->bits_per_pixel) {
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case 1:
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case 2:
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case 4:
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var->red.offset = 0;
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var->red.length = var->bits_per_pixel;
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var->green = var->red;
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var->blue = var->red;
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break;
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case 8:
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if (display->type != S3C2410_LCDCON1_TFT) {
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/* 8 bpp 332 */
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var->red.length = 3;
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var->red.offset = 5;
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var->green.length = 3;
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var->green.offset = 2;
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var->blue.length = 2;
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var->blue.offset = 0;
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} else {
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var->red.offset = 0;
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var->red.length = 8;
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var->green = var->red;
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var->blue = var->red;
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}
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break;
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case 12:
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/* 12 bpp 444 */
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var->red.length = 4;
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var->red.offset = 8;
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var->green.length = 4;
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var->green.offset = 4;
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var->blue.length = 4;
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var->blue.offset = 0;
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break;
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default:
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case 16:
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if (display->lcdcon5 & S3C2410_LCDCON5_FRM565) {
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/* 16 bpp, 565 format */
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var->red.offset = 11;
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var->green.offset = 5;
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var->blue.offset = 0;
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var->red.length = 5;
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var->green.length = 6;
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var->blue.length = 5;
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} else {
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/* 16 bpp, 5551 format */
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var->red.offset = 11;
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var->green.offset = 6;
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var->blue.offset = 1;
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var->red.length = 5;
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var->green.length = 5;
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var->blue.length = 5;
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}
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break;
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case 32:
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/* 24 bpp 888 and 8 dummy */
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var->red.length = 8;
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var->red.offset = 16;
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var->green.length = 8;
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var->green.offset = 8;
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var->blue.length = 8;
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var->blue.offset = 0;
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break;
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}
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return 0;
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}
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/* s3c2410fb_calculate_stn_lcd_regs
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*
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* calculate register values from var settings
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*/
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static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
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struct s3c2410fb_hw *regs)
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{
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const struct s3c2410fb_info *fbi = info->par;
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const struct fb_var_screeninfo *var = &info->var;
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int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT;
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int hs = var->xres >> 2;
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unsigned wdly = (var->left_margin >> 4) - 1;
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unsigned wlh = (var->hsync_len >> 4) - 1;
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if (type != S3C2410_LCDCON1_STN4)
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hs >>= 1;
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switch (var->bits_per_pixel) {
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case 1:
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regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
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break;
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case 2:
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regs->lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
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break;
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case 4:
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regs->lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
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break;
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case 8:
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regs->lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
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hs *= 3;
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break;
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case 12:
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regs->lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
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hs *= 3;
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break;
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default:
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/* invalid pixel depth */
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dev_err(fbi->dev, "invalid bpp %d\n",
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var->bits_per_pixel);
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}
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/* update X/Y info */
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dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
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var->left_margin, var->right_margin, var->hsync_len);
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regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1);
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if (wdly > 3)
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wdly = 3;
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if (wlh > 3)
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wlh = 3;
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regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) |
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S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) |
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S3C2410_LCDCON3_HOZVAL(hs - 1);
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regs->lcdcon4 = S3C2410_LCDCON4_WLH(wlh);
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}
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/* s3c2410fb_calculate_tft_lcd_regs
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*
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* calculate register values from var settings
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*/
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static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
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struct s3c2410fb_hw *regs)
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{
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const struct s3c2410fb_info *fbi = info->par;
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const struct fb_var_screeninfo *var = &info->var;
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switch (var->bits_per_pixel) {
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case 1:
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regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
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break;
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case 2:
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regs->lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
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break;
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case 4:
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regs->lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
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break;
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case 8:
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regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
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regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
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S3C2410_LCDCON5_FRM565;
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regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
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break;
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case 16:
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regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
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regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
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regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
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break;
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case 32:
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regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
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regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
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S3C2410_LCDCON5_HWSWP |
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S3C2410_LCDCON5_BPP24BL);
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break;
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default:
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/* invalid pixel depth */
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dev_err(fbi->dev, "invalid bpp %d\n",
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var->bits_per_pixel);
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}
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/* update X/Y info */
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dprintk("setting vert: up=%d, low=%d, sync=%d\n",
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var->upper_margin, var->lower_margin, var->vsync_len);
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dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
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var->left_margin, var->right_margin, var->hsync_len);
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regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1) |
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S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
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S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
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S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
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regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
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S3C2410_LCDCON3_HFPD(var->left_margin - 1) |
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S3C2410_LCDCON3_HOZVAL(var->xres - 1);
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regs->lcdcon4 = S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
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}
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/* s3c2410fb_activate_var
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*
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* activate (set) the controller from the given framebuffer
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* information
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*/
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static void s3c2410fb_activate_var(struct fb_info *info)
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{
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struct s3c2410fb_info *fbi = info->par;
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void __iomem *regs = fbi->io;
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int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
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struct fb_var_screeninfo *var = &info->var;
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int clkdiv;
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clkdiv = DIV_ROUND_UP(s3c2410fb_calc_pixclk(fbi, var->pixclock), 2);
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dprintk("%s: var->xres = %d\n", __func__, var->xres);
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dprintk("%s: var->yres = %d\n", __func__, var->yres);
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dprintk("%s: var->bpp = %d\n", __func__, var->bits_per_pixel);
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if (type == S3C2410_LCDCON1_TFT) {
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s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
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--clkdiv;
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if (clkdiv < 0)
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clkdiv = 0;
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} else {
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s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
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if (clkdiv < 2)
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clkdiv = 2;
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}
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fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
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/* write new registers */
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dprintk("new register set:\n");
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dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
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dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
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dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
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dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
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dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
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writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID,
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regs + S3C2410_LCDCON1);
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writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
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writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
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writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
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writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
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/* set lcd address pointers */
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s3c2410fb_set_lcdaddr(info);
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fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID,
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writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
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}
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/*
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* s3c2410fb_set_par - Alters the hardware state.
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* @info: frame buffer structure that represents a single frame buffer
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*
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*/
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static int s3c2410fb_set_par(struct fb_info *info)
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{
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struct fb_var_screeninfo *var = &info->var;
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switch (var->bits_per_pixel) {
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case 32:
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case 16:
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case 12:
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info->fix.visual = FB_VISUAL_TRUECOLOR;
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break;
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case 1:
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info->fix.visual = FB_VISUAL_MONO01;
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break;
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default:
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info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
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break;
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}
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info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
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/* activate this new configuration */
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s3c2410fb_activate_var(info);
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return 0;
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}
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static void schedule_palette_update(struct s3c2410fb_info *fbi,
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unsigned int regno, unsigned int val)
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{
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unsigned long flags;
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unsigned long irqen;
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void __iomem *irq_base = fbi->irq_base;
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local_irq_save(flags);
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fbi->palette_buffer[regno] = val;
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if (!fbi->palette_ready) {
|
|
fbi->palette_ready = 1;
|
|
|
|
/* enable IRQ */
|
|
irqen = readl(irq_base + S3C24XX_LCDINTMSK);
|
|
irqen &= ~S3C2410_LCDINT_FRSYNC;
|
|
writel(irqen, irq_base + S3C24XX_LCDINTMSK);
|
|
}
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
/* from pxafb.c */
|
|
static inline unsigned int chan_to_field(unsigned int chan,
|
|
struct fb_bitfield *bf)
|
|
{
|
|
chan &= 0xffff;
|
|
chan >>= 16 - bf->length;
|
|
return chan << bf->offset;
|
|
}
|
|
|
|
static int s3c2410fb_setcolreg(unsigned regno,
|
|
unsigned red, unsigned green, unsigned blue,
|
|
unsigned transp, struct fb_info *info)
|
|
{
|
|
struct s3c2410fb_info *fbi = info->par;
|
|
void __iomem *regs = fbi->io;
|
|
unsigned int val;
|
|
|
|
/* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
|
|
regno, red, green, blue); */
|
|
|
|
switch (info->fix.visual) {
|
|
case FB_VISUAL_TRUECOLOR:
|
|
/* true-colour, use pseudo-palette */
|
|
|
|
if (regno < 16) {
|
|
u32 *pal = info->pseudo_palette;
|
|
|
|
val = chan_to_field(red, &info->var.red);
|
|
val |= chan_to_field(green, &info->var.green);
|
|
val |= chan_to_field(blue, &info->var.blue);
|
|
|
|
pal[regno] = val;
|
|
}
|
|
break;
|
|
|
|
case FB_VISUAL_PSEUDOCOLOR:
|
|
if (regno < 256) {
|
|
/* currently assume RGB 5-6-5 mode */
|
|
|
|
val = (red >> 0) & 0xf800;
|
|
val |= (green >> 5) & 0x07e0;
|
|
val |= (blue >> 11) & 0x001f;
|
|
|
|
writel(val, regs + S3C2410_TFTPAL(regno));
|
|
schedule_palette_update(fbi, regno, val);
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
return 1; /* unknown type */
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* s3c2410fb_lcd_enable
|
|
*
|
|
* shutdown the lcd controller
|
|
*/
|
|
static void s3c2410fb_lcd_enable(struct s3c2410fb_info *fbi, int enable)
|
|
{
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
|
|
if (enable)
|
|
fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
|
|
else
|
|
fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
|
|
|
|
writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
|
|
/*
|
|
* s3c2410fb_blank
|
|
* @blank_mode: the blank mode we want.
|
|
* @info: frame buffer structure that represents a single frame buffer
|
|
*
|
|
* Blank the screen if blank_mode != 0, else unblank. Return 0 if
|
|
* blanking succeeded, != 0 if un-/blanking failed due to e.g. a
|
|
* video mode which doesn't support it. Implements VESA suspend
|
|
* and powerdown modes on hardware that supports disabling hsync/vsync:
|
|
*
|
|
* Returns negative errno on error, or zero on success.
|
|
*
|
|
*/
|
|
static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
|
|
{
|
|
struct s3c2410fb_info *fbi = info->par;
|
|
void __iomem *tpal_reg = fbi->io;
|
|
|
|
dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
|
|
|
|
tpal_reg += is_s3c2412(fbi) ? S3C2412_TPAL : S3C2410_TPAL;
|
|
|
|
if (blank_mode == FB_BLANK_POWERDOWN) {
|
|
s3c2410fb_lcd_enable(fbi, 0);
|
|
} else {
|
|
s3c2410fb_lcd_enable(fbi, 1);
|
|
}
|
|
|
|
if (blank_mode == FB_BLANK_UNBLANK)
|
|
writel(0x0, tpal_reg);
|
|
else {
|
|
dprintk("setting TPAL to output 0x000000\n");
|
|
writel(S3C2410_TPAL_EN, tpal_reg);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s3c2410fb_debug_show(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
|
|
}
|
|
|
|
static int s3c2410fb_debug_store(struct device *dev,
|
|
struct device_attribute *attr,
|
|
const char *buf, size_t len)
|
|
{
|
|
if (len < 1)
|
|
return -EINVAL;
|
|
|
|
if (strnicmp(buf, "on", 2) == 0 ||
|
|
strnicmp(buf, "1", 1) == 0) {
|
|
debug = 1;
|
|
printk(KERN_DEBUG "s3c2410fb: Debug On");
|
|
} else if (strnicmp(buf, "off", 3) == 0 ||
|
|
strnicmp(buf, "0", 1) == 0) {
|
|
debug = 0;
|
|
printk(KERN_DEBUG "s3c2410fb: Debug Off");
|
|
} else {
|
|
return -EINVAL;
|
|
}
|
|
|
|
return len;
|
|
}
|
|
|
|
static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store);
|
|
|
|
static struct fb_ops s3c2410fb_ops = {
|
|
.owner = THIS_MODULE,
|
|
.fb_check_var = s3c2410fb_check_var,
|
|
.fb_set_par = s3c2410fb_set_par,
|
|
.fb_blank = s3c2410fb_blank,
|
|
.fb_setcolreg = s3c2410fb_setcolreg,
|
|
.fb_fillrect = cfb_fillrect,
|
|
.fb_copyarea = cfb_copyarea,
|
|
.fb_imageblit = cfb_imageblit,
|
|
};
|
|
|
|
/*
|
|
* s3c2410fb_map_video_memory():
|
|
* Allocates the DRAM memory for the frame buffer. This buffer is
|
|
* remapped into a non-cached, non-buffered, memory region to
|
|
* allow palette and pixel writes to occur without flushing the
|
|
* cache. Once this area is remapped, all virtual memory
|
|
* access to the video memory should occur at the new region.
|
|
*/
|
|
static int __devinit s3c2410fb_map_video_memory(struct fb_info *info)
|
|
{
|
|
struct s3c2410fb_info *fbi = info->par;
|
|
dma_addr_t map_dma;
|
|
unsigned map_size = PAGE_ALIGN(info->fix.smem_len);
|
|
|
|
dprintk("map_video_memory(fbi=%p) map_size %u\n", fbi, map_size);
|
|
|
|
info->screen_base = dma_alloc_writecombine(fbi->dev, map_size,
|
|
&map_dma, GFP_KERNEL);
|
|
|
|
if (info->screen_base) {
|
|
/* prevent initial garbage on screen */
|
|
dprintk("map_video_memory: clear %p:%08x\n",
|
|
info->screen_base, map_size);
|
|
memset(info->screen_base, 0x00, map_size);
|
|
|
|
info->fix.smem_start = map_dma;
|
|
|
|
dprintk("map_video_memory: dma=%08lx cpu=%p size=%08x\n",
|
|
info->fix.smem_start, info->screen_base, map_size);
|
|
}
|
|
|
|
return info->screen_base ? 0 : -ENOMEM;
|
|
}
|
|
|
|
static inline void s3c2410fb_unmap_video_memory(struct fb_info *info)
|
|
{
|
|
struct s3c2410fb_info *fbi = info->par;
|
|
|
|
dma_free_writecombine(fbi->dev, PAGE_ALIGN(info->fix.smem_len),
|
|
info->screen_base, info->fix.smem_start);
|
|
}
|
|
|
|
static inline void modify_gpio(void __iomem *reg,
|
|
unsigned long set, unsigned long mask)
|
|
{
|
|
unsigned long tmp;
|
|
|
|
tmp = readl(reg) & ~mask;
|
|
writel(tmp | set, reg);
|
|
}
|
|
|
|
/*
|
|
* s3c2410fb_init_registers - Initialise all LCD-related registers
|
|
*/
|
|
static int s3c2410fb_init_registers(struct fb_info *info)
|
|
{
|
|
struct s3c2410fb_info *fbi = info->par;
|
|
struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
|
|
unsigned long flags;
|
|
void __iomem *regs = fbi->io;
|
|
void __iomem *tpal;
|
|
void __iomem *lpcsel;
|
|
|
|
if (is_s3c2412(fbi)) {
|
|
tpal = regs + S3C2412_TPAL;
|
|
lpcsel = regs + S3C2412_TCONSEL;
|
|
} else {
|
|
tpal = regs + S3C2410_TPAL;
|
|
lpcsel = regs + S3C2410_LPCSEL;
|
|
}
|
|
|
|
/* Initialise LCD with values from haret */
|
|
|
|
local_irq_save(flags);
|
|
|
|
/* modify the gpio(s) with interrupts set (bjd) */
|
|
|
|
modify_gpio(S3C2410_GPCUP, mach_info->gpcup, mach_info->gpcup_mask);
|
|
modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
|
|
modify_gpio(S3C2410_GPDUP, mach_info->gpdup, mach_info->gpdup_mask);
|
|
modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
|
|
|
|
local_irq_restore(flags);
|
|
|
|
dprintk("LPCSEL = 0x%08lx\n", mach_info->lpcsel);
|
|
writel(mach_info->lpcsel, lpcsel);
|
|
|
|
dprintk("replacing TPAL %08x\n", readl(tpal));
|
|
|
|
/* ensure temporary palette disabled */
|
|
writel(0x00, tpal);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
|
|
{
|
|
unsigned int i;
|
|
void __iomem *regs = fbi->io;
|
|
|
|
fbi->palette_ready = 0;
|
|
|
|
for (i = 0; i < 256; i++) {
|
|
unsigned long ent = fbi->palette_buffer[i];
|
|
if (ent == PALETTE_BUFF_CLEAR)
|
|
continue;
|
|
|
|
writel(ent, regs + S3C2410_TFTPAL(i));
|
|
|
|
/* it seems the only way to know exactly
|
|
* if the palette wrote ok, is to check
|
|
* to see if the value verifies ok
|
|
*/
|
|
|
|
if (readw(regs + S3C2410_TFTPAL(i)) == ent)
|
|
fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
|
|
else
|
|
fbi->palette_ready = 1; /* retry */
|
|
}
|
|
}
|
|
|
|
static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
|
|
{
|
|
struct s3c2410fb_info *fbi = dev_id;
|
|
void __iomem *irq_base = fbi->irq_base;
|
|
unsigned long lcdirq = readl(irq_base + S3C24XX_LCDINTPND);
|
|
|
|
if (lcdirq & S3C2410_LCDINT_FRSYNC) {
|
|
if (fbi->palette_ready)
|
|
s3c2410fb_write_palette(fbi);
|
|
|
|
writel(S3C2410_LCDINT_FRSYNC, irq_base + S3C24XX_LCDINTPND);
|
|
writel(S3C2410_LCDINT_FRSYNC, irq_base + S3C24XX_LCDSRCPND);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
#ifdef CONFIG_CPU_FREQ
|
|
|
|
static int s3c2410fb_cpufreq_transition(struct notifier_block *nb,
|
|
unsigned long val, void *data)
|
|
{
|
|
struct cpufreq_freqs *freqs = data;
|
|
struct s3c2410fb_info *info;
|
|
struct fb_info *fbinfo;
|
|
long delta_f;
|
|
|
|
info = container_of(nb, struct s3c2410fb_info, freq_transition);
|
|
fbinfo = platform_get_drvdata(to_platform_device(info->dev));
|
|
|
|
/* work out change, <0 for speed-up */
|
|
delta_f = info->clk_rate - clk_get_rate(info->clk);
|
|
|
|
if ((val == CPUFREQ_POSTCHANGE && delta_f > 0) ||
|
|
(val == CPUFREQ_PRECHANGE && delta_f < 0)) {
|
|
info->clk_rate = clk_get_rate(info->clk);
|
|
s3c2410fb_activate_var(fbinfo);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info *info)
|
|
{
|
|
info->freq_transition.notifier_call = s3c2410fb_cpufreq_transition;
|
|
|
|
return cpufreq_register_notifier(&info->freq_transition,
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
}
|
|
|
|
static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info *info)
|
|
{
|
|
cpufreq_unregister_notifier(&info->freq_transition,
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
}
|
|
|
|
#else
|
|
static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info *info)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info *info)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
|
|
static char driver_name[] = "s3c2410fb";
|
|
|
|
static int __devinit s3c24xxfb_probe(struct platform_device *pdev,
|
|
enum s3c_drv_type drv_type)
|
|
{
|
|
struct s3c2410fb_info *info;
|
|
struct s3c2410fb_display *display;
|
|
struct fb_info *fbinfo;
|
|
struct s3c2410fb_mach_info *mach_info;
|
|
struct resource *res;
|
|
int ret;
|
|
int irq;
|
|
int i;
|
|
int size;
|
|
u32 lcdcon1;
|
|
|
|
mach_info = pdev->dev.platform_data;
|
|
if (mach_info == NULL) {
|
|
dev_err(&pdev->dev,
|
|
"no platform data for lcd, cannot attach\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (mach_info->default_display >= mach_info->num_displays) {
|
|
dev_err(&pdev->dev, "default is %d but only %d displays\n",
|
|
mach_info->default_display, mach_info->num_displays);
|
|
return -EINVAL;
|
|
}
|
|
|
|
display = mach_info->displays + mach_info->default_display;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "no irq for device\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
|
|
if (!fbinfo)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, fbinfo);
|
|
|
|
info = fbinfo->par;
|
|
info->dev = &pdev->dev;
|
|
info->drv_type = drv_type;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (res == NULL) {
|
|
dev_err(&pdev->dev, "failed to get memory registers\n");
|
|
ret = -ENXIO;
|
|
goto dealloc_fb;
|
|
}
|
|
|
|
size = resource_size(res);
|
|
info->mem = request_mem_region(res->start, size, pdev->name);
|
|
if (info->mem == NULL) {
|
|
dev_err(&pdev->dev, "failed to get memory region\n");
|
|
ret = -ENOENT;
|
|
goto dealloc_fb;
|
|
}
|
|
|
|
info->io = ioremap(res->start, size);
|
|
if (info->io == NULL) {
|
|
dev_err(&pdev->dev, "ioremap() of registers failed\n");
|
|
ret = -ENXIO;
|
|
goto release_mem;
|
|
}
|
|
|
|
info->irq_base = info->io + ((drv_type == DRV_S3C2412) ? S3C2412_LCDINTBASE : S3C2410_LCDINTBASE);
|
|
|
|
dprintk("devinit\n");
|
|
|
|
strcpy(fbinfo->fix.id, driver_name);
|
|
|
|
/* Stop the video */
|
|
lcdcon1 = readl(info->io + S3C2410_LCDCON1);
|
|
writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
|
|
|
|
fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
|
|
fbinfo->fix.type_aux = 0;
|
|
fbinfo->fix.xpanstep = 0;
|
|
fbinfo->fix.ypanstep = 0;
|
|
fbinfo->fix.ywrapstep = 0;
|
|
fbinfo->fix.accel = FB_ACCEL_NONE;
|
|
|
|
fbinfo->var.nonstd = 0;
|
|
fbinfo->var.activate = FB_ACTIVATE_NOW;
|
|
fbinfo->var.accel_flags = 0;
|
|
fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
|
|
|
|
fbinfo->fbops = &s3c2410fb_ops;
|
|
fbinfo->flags = FBINFO_FLAG_DEFAULT;
|
|
fbinfo->pseudo_palette = &info->pseudo_pal;
|
|
|
|
for (i = 0; i < 256; i++)
|
|
info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
|
|
|
|
ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
|
|
ret = -EBUSY;
|
|
goto release_regs;
|
|
}
|
|
|
|
info->clk = clk_get(NULL, "lcd");
|
|
if (IS_ERR(info->clk)) {
|
|
printk(KERN_ERR "failed to get lcd clock source\n");
|
|
ret = PTR_ERR(info->clk);
|
|
goto release_irq;
|
|
}
|
|
|
|
clk_enable(info->clk);
|
|
dprintk("got and enabled clock\n");
|
|
|
|
msleep(1);
|
|
|
|
info->clk_rate = clk_get_rate(info->clk);
|
|
|
|
/* find maximum required memory size for display */
|
|
for (i = 0; i < mach_info->num_displays; i++) {
|
|
unsigned long smem_len = mach_info->displays[i].xres;
|
|
|
|
smem_len *= mach_info->displays[i].yres;
|
|
smem_len *= mach_info->displays[i].bpp;
|
|
smem_len >>= 3;
|
|
if (fbinfo->fix.smem_len < smem_len)
|
|
fbinfo->fix.smem_len = smem_len;
|
|
}
|
|
|
|
/* Initialize video memory */
|
|
ret = s3c2410fb_map_video_memory(fbinfo);
|
|
if (ret) {
|
|
printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
|
|
ret = -ENOMEM;
|
|
goto release_clock;
|
|
}
|
|
|
|
dprintk("got video memory\n");
|
|
|
|
fbinfo->var.xres = display->xres;
|
|
fbinfo->var.yres = display->yres;
|
|
fbinfo->var.bits_per_pixel = display->bpp;
|
|
|
|
s3c2410fb_init_registers(fbinfo);
|
|
|
|
s3c2410fb_check_var(&fbinfo->var, fbinfo);
|
|
|
|
ret = s3c2410fb_cpufreq_register(info);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Failed to register cpufreq\n");
|
|
goto free_video_memory;
|
|
}
|
|
|
|
ret = register_framebuffer(fbinfo);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "Failed to register framebuffer device: %d\n",
|
|
ret);
|
|
goto free_cpufreq;
|
|
}
|
|
|
|
/* create device files */
|
|
ret = device_create_file(&pdev->dev, &dev_attr_debug);
|
|
if (ret) {
|
|
printk(KERN_ERR "failed to add debug attribute\n");
|
|
}
|
|
|
|
printk(KERN_INFO "fb%d: %s frame buffer device\n",
|
|
fbinfo->node, fbinfo->fix.id);
|
|
|
|
return 0;
|
|
|
|
free_cpufreq:
|
|
s3c2410fb_cpufreq_deregister(info);
|
|
free_video_memory:
|
|
s3c2410fb_unmap_video_memory(fbinfo);
|
|
release_clock:
|
|
clk_disable(info->clk);
|
|
clk_put(info->clk);
|
|
release_irq:
|
|
free_irq(irq, info);
|
|
release_regs:
|
|
iounmap(info->io);
|
|
release_mem:
|
|
release_mem_region(res->start, size);
|
|
dealloc_fb:
|
|
platform_set_drvdata(pdev, NULL);
|
|
framebuffer_release(fbinfo);
|
|
return ret;
|
|
}
|
|
|
|
static int __devinit s3c2410fb_probe(struct platform_device *pdev)
|
|
{
|
|
return s3c24xxfb_probe(pdev, DRV_S3C2410);
|
|
}
|
|
|
|
static int __devinit s3c2412fb_probe(struct platform_device *pdev)
|
|
{
|
|
return s3c24xxfb_probe(pdev, DRV_S3C2412);
|
|
}
|
|
|
|
|
|
/*
|
|
* Cleanup
|
|
*/
|
|
static int __devexit s3c2410fb_remove(struct platform_device *pdev)
|
|
{
|
|
struct fb_info *fbinfo = platform_get_drvdata(pdev);
|
|
struct s3c2410fb_info *info = fbinfo->par;
|
|
int irq;
|
|
|
|
unregister_framebuffer(fbinfo);
|
|
s3c2410fb_cpufreq_deregister(info);
|
|
|
|
s3c2410fb_lcd_enable(info, 0);
|
|
msleep(1);
|
|
|
|
s3c2410fb_unmap_video_memory(fbinfo);
|
|
|
|
if (info->clk) {
|
|
clk_disable(info->clk);
|
|
clk_put(info->clk);
|
|
info->clk = NULL;
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
free_irq(irq, info);
|
|
|
|
iounmap(info->io);
|
|
|
|
release_mem_region(info->mem->start, resource_size(info->mem));
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
framebuffer_release(fbinfo);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
/* suspend and resume support for the lcd controller */
|
|
static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
|
|
{
|
|
struct fb_info *fbinfo = platform_get_drvdata(dev);
|
|
struct s3c2410fb_info *info = fbinfo->par;
|
|
|
|
s3c2410fb_lcd_enable(info, 0);
|
|
|
|
/* sleep before disabling the clock, we need to ensure
|
|
* the LCD DMA engine is not going to get back on the bus
|
|
* before the clock goes off again (bjd) */
|
|
|
|
msleep(1);
|
|
clk_disable(info->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s3c2410fb_resume(struct platform_device *dev)
|
|
{
|
|
struct fb_info *fbinfo = platform_get_drvdata(dev);
|
|
struct s3c2410fb_info *info = fbinfo->par;
|
|
|
|
clk_enable(info->clk);
|
|
msleep(1);
|
|
|
|
s3c2410fb_init_registers(fbinfo);
|
|
|
|
/* re-activate our display after resume */
|
|
s3c2410fb_activate_var(fbinfo);
|
|
s3c2410fb_blank(FB_BLANK_UNBLANK, fbinfo);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#else
|
|
#define s3c2410fb_suspend NULL
|
|
#define s3c2410fb_resume NULL
|
|
#endif
|
|
|
|
static struct platform_driver s3c2410fb_driver = {
|
|
.probe = s3c2410fb_probe,
|
|
.remove = __devexit_p(s3c2410fb_remove),
|
|
.suspend = s3c2410fb_suspend,
|
|
.resume = s3c2410fb_resume,
|
|
.driver = {
|
|
.name = "s3c2410-lcd",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static struct platform_driver s3c2412fb_driver = {
|
|
.probe = s3c2412fb_probe,
|
|
.remove = __devexit_p(s3c2410fb_remove),
|
|
.suspend = s3c2410fb_suspend,
|
|
.resume = s3c2410fb_resume,
|
|
.driver = {
|
|
.name = "s3c2412-lcd",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
int __init s3c2410fb_init(void)
|
|
{
|
|
int ret = platform_driver_register(&s3c2410fb_driver);
|
|
|
|
if (ret == 0)
|
|
ret = platform_driver_register(&s3c2412fb_driver);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void __exit s3c2410fb_cleanup(void)
|
|
{
|
|
platform_driver_unregister(&s3c2410fb_driver);
|
|
platform_driver_unregister(&s3c2412fb_driver);
|
|
}
|
|
|
|
module_init(s3c2410fb_init);
|
|
module_exit(s3c2410fb_cleanup);
|
|
|
|
MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
|
|
"Ben Dooks <ben-linux@fluff.org>");
|
|
MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:s3c2410-lcd");
|
|
MODULE_ALIAS("platform:s3c2412-lcd");
|