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![Pádraig Brady](/assets/img/avatar_default.png)
For TCO V1 devices the programmed timeout was twice too long because the fact that the TCO V1 timer needs to count down twice before triggering the watchdog, wasn't accounted for. Also the timeout values in the module description and error message were clarified. And the _STS registers are 16 bit instead of 8 bit. Signed-off-by: Pádraig Brady <P@draigBrady.com> Tested-by: Simon Kagstrom <simon.kagstrom@netinsight.se> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
375 lines
11 KiB
C
375 lines
11 KiB
C
/*
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* intel TCO vendor specific watchdog driver support
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*
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* (c) Copyright 2006-2009 Wim Van Sebroeck <wim@iguana.be>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
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* provide warranty for any of this software. This material is
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* provided "AS-IS" and at no charge.
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*/
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/*
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* Includes, defines, variables, module parameters, ...
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*/
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/* Module and version information */
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#define DRV_NAME "iTCO_vendor_support"
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#define DRV_VERSION "1.04"
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#define PFX DRV_NAME ": "
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/* Includes */
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#include <linux/module.h> /* For module specific items */
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#include <linux/moduleparam.h> /* For new moduleparam's */
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#include <linux/types.h> /* For standard types (like size_t) */
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#include <linux/errno.h> /* For the -ENODEV/... values */
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#include <linux/kernel.h> /* For printk/panic/... */
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#include <linux/init.h> /* For __init/__exit/... */
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#include <linux/ioport.h> /* For io-port access */
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#include <linux/io.h> /* For inb/outb/... */
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#include "iTCO_vendor.h"
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/* iTCO defines */
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#define SMI_EN (acpibase + 0x30) /* SMI Control and Enable Register */
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#define TCOBASE (acpibase + 0x60) /* TCO base address */
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#define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
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/* List of vendor support modes */
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/* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */
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#define SUPERMICRO_OLD_BOARD 1
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/* SuperMicro Pentium 4 / Xeon 4 / EMT64T Era Systems */
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#define SUPERMICRO_NEW_BOARD 2
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/* Broken BIOS */
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#define BROKEN_BIOS 911
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static int vendorsupport;
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module_param(vendorsupport, int, 0);
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MODULE_PARM_DESC(vendorsupport, "iTCO vendor specific support mode, default="
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"0 (none), 1=SuperMicro Pent3, 2=SuperMicro Pent4+, "
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"911=Broken SMI BIOS");
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/*
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* Vendor Specific Support
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*/
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/*
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* Vendor Support: 1
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* Board: Super Micro Computer Inc. 370SSE+-OEM1/P3TSSE
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* iTCO chipset: ICH2
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*
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* Code contributed by: R. Seretny <lkpatches@paypc.com>
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* Documentation obtained by R. Seretny from SuperMicro Technical Support
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*
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* To enable Watchdog function:
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* BIOS setup -> Power -> TCO Logic SMI Enable -> Within5Minutes
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* This setting enables SMI to clear the watchdog expired flag.
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* If BIOS or CPU fail which may cause SMI hang, then system will
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* reboot. When application starts to use watchdog function,
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* application has to take over the control from SMI.
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*
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* For P3TSSE, J36 jumper needs to be removed to enable the Watchdog
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* function.
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*
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* Note: The system will reboot when Expire Flag is set TWICE.
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* So, if the watchdog timer is 20 seconds, then the maximum hang
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* time is about 40 seconds, and the minimum hang time is about
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* 20.6 seconds.
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*/
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static void supermicro_old_pre_start(unsigned long acpibase)
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{
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unsigned long val32;
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/* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */
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val32 = inl(SMI_EN);
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val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
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outl(val32, SMI_EN); /* Needed to activate watchdog */
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}
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static void supermicro_old_pre_stop(unsigned long acpibase)
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{
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unsigned long val32;
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/* Bit 13: TCO_EN -> 1 = Enables the TCO logic to generate SMI# */
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val32 = inl(SMI_EN);
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val32 |= 0x00002000; /* Turn on SMI clearing watchdog */
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outl(val32, SMI_EN); /* Needed to deactivate watchdog */
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}
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/*
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* Vendor Support: 2
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* Board: Super Micro Computer Inc. P4SBx, P4DPx
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* iTCO chipset: ICH4
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*
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* Code contributed by: R. Seretny <lkpatches@paypc.com>
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* Documentation obtained by R. Seretny from SuperMicro Technical Support
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*
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* To enable Watchdog function:
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* 1. BIOS
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* For P4SBx:
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* BIOS setup -> Advanced -> Integrated Peripherals -> Watch Dog Feature
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* For P4DPx:
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* BIOS setup -> Advanced -> I/O Device Configuration -> Watch Dog
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* This setting enables or disables Watchdog function. When enabled, the
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* default watchdog timer is set to be 5 minutes (about 4m35s). It is
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* enough to load and run the OS. The application (service or driver) has
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* to take over the control once OS is running up and before watchdog
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* expires.
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*
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* 2. JUMPER
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* For P4SBx: JP39
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* For P4DPx: JP37
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* This jumper is used for safety. Closed is enabled. This jumper
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* prevents user enables watchdog in BIOS by accident.
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*
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* To enable Watch Dog function, both BIOS and JUMPER must be enabled.
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*
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* The documentation lists motherboards P4SBx and P4DPx series as of
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* 20-March-2002. However, this code works flawlessly with much newer
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* motherboards, such as my X6DHR-8G2 (SuperServer 6014H-82).
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*
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* The original iTCO driver as written does not actually reset the
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* watchdog timer on these machines, as a result they reboot after five
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* minutes.
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*
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* NOTE: You may leave the Watchdog function disabled in the SuperMicro
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* BIOS to avoid a "boot-race"... This driver will enable watchdog
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* functionality even if it's disabled in the BIOS once the /dev/watchdog
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* file is opened.
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*/
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/* I/O Port's */
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#define SM_REGINDEX 0x2e /* SuperMicro ICH4+ Register Index */
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#define SM_DATAIO 0x2f /* SuperMicro ICH4+ Register Data I/O */
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/* Control Register's */
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#define SM_CTLPAGESW 0x07 /* SuperMicro ICH4+ Control Page Switch */
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#define SM_CTLPAGE 0x08 /* SuperMicro ICH4+ Control Page Num */
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#define SM_WATCHENABLE 0x30 /* Watchdog enable: Bit 0: 0=off, 1=on */
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#define SM_WATCHPAGE 0x87 /* Watchdog unlock control page */
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#define SM_ENDWATCH 0xAA /* Watchdog lock control page */
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#define SM_COUNTMODE 0xf5 /* Watchdog count mode select */
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/* (Bit 3: 0 = seconds, 1 = minutes */
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#define SM_WATCHTIMER 0xf6 /* 8-bits, Watchdog timer counter (RW) */
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#define SM_RESETCONTROL 0xf7 /* Watchdog reset control */
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/* Bit 6: timer is reset by kbd interrupt */
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/* Bit 7: timer is reset by mouse interrupt */
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static void supermicro_new_unlock_watchdog(void)
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{
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/* Write 0x87 to port 0x2e twice */
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outb(SM_WATCHPAGE, SM_REGINDEX);
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outb(SM_WATCHPAGE, SM_REGINDEX);
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/* Switch to watchdog control page */
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outb(SM_CTLPAGESW, SM_REGINDEX);
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outb(SM_CTLPAGE, SM_DATAIO);
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}
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static void supermicro_new_lock_watchdog(void)
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{
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outb(SM_ENDWATCH, SM_REGINDEX);
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}
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static void supermicro_new_pre_start(unsigned int heartbeat)
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{
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unsigned int val;
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supermicro_new_unlock_watchdog();
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/* Watchdog timer setting needs to be in seconds*/
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outb(SM_COUNTMODE, SM_REGINDEX);
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val = inb(SM_DATAIO);
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val &= 0xF7;
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outb(val, SM_DATAIO);
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/* Write heartbeat interval to WDOG */
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outb(SM_WATCHTIMER, SM_REGINDEX);
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outb((heartbeat & 255), SM_DATAIO);
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/* Make sure keyboard/mouse interrupts don't interfere */
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outb(SM_RESETCONTROL, SM_REGINDEX);
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val = inb(SM_DATAIO);
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val &= 0x3f;
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outb(val, SM_DATAIO);
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/* enable watchdog by setting bit 0 of Watchdog Enable to 1 */
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outb(SM_WATCHENABLE, SM_REGINDEX);
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val = inb(SM_DATAIO);
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val |= 0x01;
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outb(val, SM_DATAIO);
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supermicro_new_lock_watchdog();
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}
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static void supermicro_new_pre_stop(void)
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{
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unsigned int val;
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supermicro_new_unlock_watchdog();
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/* disable watchdog by setting bit 0 of Watchdog Enable to 0 */
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outb(SM_WATCHENABLE, SM_REGINDEX);
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val = inb(SM_DATAIO);
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val &= 0xFE;
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outb(val, SM_DATAIO);
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supermicro_new_lock_watchdog();
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}
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static void supermicro_new_pre_set_heartbeat(unsigned int heartbeat)
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{
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supermicro_new_unlock_watchdog();
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/* reset watchdog timeout to heartveat value */
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outb(SM_WATCHTIMER, SM_REGINDEX);
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outb((heartbeat & 255), SM_DATAIO);
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supermicro_new_lock_watchdog();
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}
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/*
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* Vendor Support: 911
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* Board: Some Intel ICHx based motherboards
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* iTCO chipset: ICH7+
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*
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* Some Intel motherboards have a broken BIOS implementation: i.e.
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* the SMI handler clear's the TIMEOUT bit in the TC01_STS register
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* and does not reload the time. Thus the TCO watchdog does not reboot
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* the system.
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*
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* These are the conclusions of Andriy Gapon <avg@icyb.net.ua> after
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* debugging: the SMI handler is quite simple - it tests value in
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* TCO1_CNT against 0x800, i.e. checks TCO_TMR_HLT. If the bit is set
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* the handler goes into an infinite loop, apparently to allow the
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* second timeout and reboot. Otherwise it simply clears TIMEOUT bit
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* in TCO1_STS and that's it.
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* So the logic seems to be reversed, because it is hard to see how
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* TIMEOUT can get set to 1 and SMI generated when TCO_TMR_HLT is set
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* (other than a transitional effect).
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*
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* The only fix found to get the motherboard(s) to reboot is to put
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* the glb_smi_en bit to 0. This is a dirty hack that bypasses the
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* broken code by disabling Global SMI.
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*
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* WARNING: globally disabling SMI could possibly lead to dramatic
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* problems, especially on laptops! I.e. various ACPI things where
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* SMI is used for communication between OS and firmware.
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*
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* Don't use this fix if you don't need to!!!
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*/
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static void broken_bios_start(unsigned long acpibase)
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{
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unsigned long val32;
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val32 = inl(SMI_EN);
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/* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI#
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Bit 0: GBL_SMI_EN -> 0 = No SMI# will be generated by ICH. */
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val32 &= 0xffffdffe;
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outl(val32, SMI_EN);
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}
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static void broken_bios_stop(unsigned long acpibase)
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{
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unsigned long val32;
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val32 = inl(SMI_EN);
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/* Bit 13: TCO_EN -> 1 = Enables TCO logic generating an SMI#
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Bit 0: GBL_SMI_EN -> 1 = Turn global SMI on again. */
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val32 |= 0x00002001;
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outl(val32, SMI_EN);
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}
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/*
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* Generic Support Functions
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*/
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void iTCO_vendor_pre_start(unsigned long acpibase,
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unsigned int heartbeat)
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{
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switch (vendorsupport) {
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case SUPERMICRO_OLD_BOARD:
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supermicro_old_pre_start(acpibase);
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break;
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case SUPERMICRO_NEW_BOARD:
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supermicro_new_pre_start(heartbeat);
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break;
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case BROKEN_BIOS:
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broken_bios_start(acpibase);
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break;
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}
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}
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EXPORT_SYMBOL(iTCO_vendor_pre_start);
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void iTCO_vendor_pre_stop(unsigned long acpibase)
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{
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switch (vendorsupport) {
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case SUPERMICRO_OLD_BOARD:
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supermicro_old_pre_stop(acpibase);
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break;
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case SUPERMICRO_NEW_BOARD:
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supermicro_new_pre_stop();
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break;
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case BROKEN_BIOS:
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broken_bios_stop(acpibase);
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break;
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}
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}
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EXPORT_SYMBOL(iTCO_vendor_pre_stop);
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void iTCO_vendor_pre_keepalive(unsigned long acpibase, unsigned int heartbeat)
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{
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if (vendorsupport == SUPERMICRO_NEW_BOARD)
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supermicro_new_pre_set_heartbeat(heartbeat);
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}
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EXPORT_SYMBOL(iTCO_vendor_pre_keepalive);
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void iTCO_vendor_pre_set_heartbeat(unsigned int heartbeat)
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{
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if (vendorsupport == SUPERMICRO_NEW_BOARD)
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supermicro_new_pre_set_heartbeat(heartbeat);
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}
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EXPORT_SYMBOL(iTCO_vendor_pre_set_heartbeat);
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int iTCO_vendor_check_noreboot_on(void)
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{
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switch (vendorsupport) {
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case SUPERMICRO_OLD_BOARD:
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return 0;
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default:
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return 1;
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}
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}
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EXPORT_SYMBOL(iTCO_vendor_check_noreboot_on);
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static int __init iTCO_vendor_init_module(void)
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{
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printk(KERN_INFO PFX "vendor-support=%d\n", vendorsupport);
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return 0;
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}
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static void __exit iTCO_vendor_exit_module(void)
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{
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printk(KERN_INFO PFX "Module Unloaded\n");
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}
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module_init(iTCO_vendor_init_module);
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module_exit(iTCO_vendor_exit_module);
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MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>, "
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"R. Seretny <lkpatches@paypc.com>");
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MODULE_DESCRIPTION("Intel TCO Vendor Specific WatchDog Timer Driver Support");
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MODULE_VERSION(DRV_VERSION);
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MODULE_LICENSE("GPL");
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