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5108de0ae0
hungarian notation will be removed from the elements inside structures, the next varibles will be renamed: Original: Replacement: dw_dsp_base_addr dsp_base_addr dw_dmmu_base dmmu_base dw_index index dw_int_addr int_addr dw_internal_size internal_size dw_last_output last_output dw_mem_base mem_base dw_mem_length mem_length dw_mem_phys mem_phys dw_mode mode dw_num_chnls num_chnls dw_offset_for_monitor offset_for_monitor dw_output_mask output_mask dw_page_size page_size dw_pa pa dw_per_base per_base dw_per_pm_base per_pm_base dw_public_rhea public_rhea dw_seg_base_pa seg_base_pa Signed-off-by: Rene Sapiens <rene.sapiens@ti.com> Signed-off-by: Armando Uribe <x0095078@ti.com> Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
61 lines
1.8 KiB
C
61 lines
1.8 KiB
C
/*
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* cfgdefs.h
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*
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* DSP-BIOS Bridge driver support functions for TI OMAP processors.
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*
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* Global CFG constants and types, shared between DSP API and Bridge driver.
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*
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* Copyright (C) 2005-2006 Texas Instruments, Inc.
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*
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* This package is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*/
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#ifndef CFGDEFS_
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#define CFGDEFS_
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/* Host Resources: */
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#define CFG_MAXMEMREGISTERS 9
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/* IRQ flag */
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#define CFG_IRQSHARED 0x01 /* IRQ can be shared */
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/* A platform-related device handle: */
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struct cfg_devnode;
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/*
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* Host resource structure.
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*/
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struct cfg_hostres {
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u32 num_mem_windows; /* Set to default */
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/* This is the base.memory */
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u32 mem_base[CFG_MAXMEMREGISTERS]; /* shm virtual address */
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u32 mem_length[CFG_MAXMEMREGISTERS]; /* Length of the Base */
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u32 mem_phys[CFG_MAXMEMREGISTERS]; /* shm Physical address */
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u8 birq_registers; /* IRQ Number */
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u8 birq_attrib; /* IRQ Attribute */
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u32 offset_for_monitor; /* The Shared memory starts from
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* mem_base + this offset */
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/*
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* Info needed by NODE for allocating channels to communicate with RMS:
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* chnl_offset: Offset of RMS channels. Lower channels are
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* reserved.
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* chnl_buf_size: Size of channel buffer to send to RMS
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* num_chnls: Total number of channels
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* (including reserved).
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*/
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u32 chnl_offset;
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u32 chnl_buf_size;
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u32 num_chnls;
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void __iomem *per_base;
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u32 per_pm_base;
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u32 core_pm_base;
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void __iomem *dmmu_base;
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};
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#endif /* CFGDEFS_ */
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