Conor Dooley ac474f4964 dt-bindings: riscv: fix SiFive l2-cache's cache-sets ... commit b60cf8e59e upstream. Fix device tree schema validation error messages for the SiFive Unmatched: ' cache-sets:0:0: 1024 was expected'. The existing bindings allow for just 1024 cache-sets but the fu740 on Unmatched the has 2048 cache-sets. The ISA itself permits any arbitrary power of two, however this is not supported by dt-schema. The RTL for the IP, to which the number of cache-sets is a tunable parameter, has been released publicly so speculatively adding a small number of "reasonable" values seems unwise also. Instead, as the binding only supports two distinct controllers: add 2048 and explicitly lock it to the fu740's l2 cache while limiting 1024 to the l2 cache on the fu540. Fixes: af951c3a11 ("dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740") Reported-by: Atul Khare <atulkhare@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220803185359.942928-1-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2022-08-17 14:40:10 +02:00
..
bindings	dt-bindings: riscv: fix SiFive l2-cache's cache-sets	2022-08-17 14:40:10 +02:00
changesets.rst
dynamic-resolution-notes.rst
index.rst
kernel-api.rst
of_unittest.rst	of: unittest: add program to process EXPECT messages	2022-02-28 15:20:32 -06:00
overlay-notes.rst
usage-model.rst