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a4b2e6063c
In case the tap delay required by Arasan SDHCI is set to 0, the current embeddedsw firmware unconditionally writes IOU_SLCR SD_ITAPDLY to 0x100 (SD0_ITAPDLYENA=1, SD0_ITAPDLYSEL=0). Previous behavior was to keep the IOU_SLCR SD_ITAPDLY set to 0x0. There is some sort of difference in the behavior between SD0_ITAPDLYENA=1/0 with the same SD0_ITAPDLYSEL=0, even though the behavior should be identical -- zero delay added to rxclk_in line. The former breaks HS200 training in low temperature conditions. Write IOU_SLCR SD_ITAPDLY register to 0 using PM_MMIO_WRITE which seem to allow unrestricted WRITE access (and PM_MMIO_READ which allows read access) to the entire address space. This way, it is possible to work around the defect in IOCTL_SET_SD_TAPDELAY design which does not permit clearing SDx_ITAPDLYENA bit. Note that the embeddedsw firmware does not permit clearing the SD_ITAPDLY SD0_ITAPDLYENA bit, this bit can only ever be set by the firmware and it is often impossible to update the possibly broken firmware. Signed-off-by: Marek Vasut <marex@denx.de> Link: https://lore.kernel.org/r/20221215152023.8387-1-marex@denx.de Signed-off-by: Michal Simek <michal.simek@amd.com> |
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| .. | ||
| arm_ffa | ||
| arm_scmi | ||
| broadcom | ||
| cirrus | ||
| efi | ||
| imx | ||
| meson | ||
| psci | ||
| smccc | ||
| tegra | ||
| xilinx | ||
| arm_scpi.c | ||
| arm_sdei.c | ||
| dmi-id.c | ||
| dmi-sysfs.c | ||
| dmi_scan.c | ||
| edd.c | ||
| iscsi_ibft.c | ||
| iscsi_ibft_find.c | ||
| Kconfig | ||
| Makefile | ||
| memmap.c | ||
| mtk-adsp-ipc.c | ||
| pcdp.c | ||
| pcdp.h | ||
| qcom_scm-legacy.c | ||
| qcom_scm-smc.c | ||
| qcom_scm.c | ||
| qcom_scm.h | ||
| qemu_fw_cfg.c | ||
| raspberrypi.c | ||
| scpi_pm_domain.c | ||
| stratix10-rsu.c | ||
| stratix10-svc.c | ||
| sysfb.c | ||
| sysfb_simplefb.c | ||
| ti_sci.c | ||
| ti_sci.h | ||
| trusted_foundations.c | ||
| turris-mox-rwtm.c | ||