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825f4e0271
A quite large set of SoC updates this cycle. In no particular order: - Multi-cluster power management for Samsung Exynos, adding support for big.LITTLE CPU switching on EXYNOS5 - SMP support for Marvell Armada 375 and 38x - SMP rework on Allwinner A31 - Xilinx Zynq support for SOC_BUS, big endian - Marvell orion5x platform cleanup, modernizing the implementation and moving to DT. - _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so that their platform can be enabled in the same kernel binary as most of the other v7 platforms in the tree. \o/ The work isn't quite complete, there's some driver fixes still needed, but the basics now work. New SoC support added: - Freescale i.MX6SX - LSI Axxia AXM55xx SoCs - Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800 - STi STIH407 Plus a large set of various smaller updates for different platforms. I'm probably missing some important one here. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJTjOKWAAoJEIwa5zzehBx36aEP/2vTD7x9FC59FACNHJ8iO7aw 0ebTgBBjI1Np6X18O+M7URbxV5TaBgwpUm/NDN86p03MpQ2eOXr8r47qVxe/HhZs AdlTvzgE6QwxcVL/HeCKKUEN3BPH74+TZgFl9I5aSzNjpR39xETeK1aWP/ZiAl/q /lGRZAQ59+c7Ung00Hg0g2YDxH9WFpK50Nj90ROnyjKSFkhIYngXYVpZB3maOypq Pgib/U8IraKZ52oGJw3yinSoORr7FdcUdAGWGTz/lQdNL/jYDfQ6GkRW2oblWXdt 3Xvj9UW6NmkbMICucMvFuuW1nXAgutZuTp9w7mBxsiUlYepxPv/DXM6yiI1WGlEb BeVOmOreNeN2nT6avv/uUhk3Osq63Jn9x8cz5y+7/lgWQwllh3/c+G01RotvgJEQ vpQq5ps9fMxIAMaNP6N/YqMJI1IOrBj0iXxaZEDw3VYM/k4lSvtb3VXP9c/rqApu U4i6hpSIGzrraU4NrjndYPndcLeNOVZbByETQKosZXuCo6G1sb7FstNSkzI9vSo8 O/pujIVUfYyBW82GzZGDw+aa7DWA29FPeUQ3p+sj5MSCg051xXT8h6QwqMo2K/zY 5ATs/qo6w7zH/Ou9rtHTRynCIb0GQJThDSlWtuXFedUF9quEltS+TDz/2o+dWtGJ yBFGKDRuBB20D36w9xqg =6LYI -----END PGP SIGNATURE----- Merge tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next Pull part one of ARM SoC updates from Olof Johansson: "A quite large set of SoC updates this cycle. In no particular order: - Multi-cluster power management for Samsung Exynos, adding support for big.LITTLE CPU switching on EXYNOS5 - SMP support for Marvell Armada 375 and 38x - SMP rework on Allwinner A31 - Xilinx Zynq support for SOC_BUS, big endian - Marvell orion5x platform cleanup, modernizing the implementation and moving to DT. - _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so that their platform can be enabled in the same kernel binary as most of the other v7 platforms in the tree. \o/ The work isn't quite complete, there's some driver fixes still needed, but the basics now work. New SoC support added: - Freescale i.MX6SX - LSI Axxia AXM55xx SoCs - Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800 - STi STIH407 plus a large set of various smaller updates for different platforms. I'm probably missing some important one here" * tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (281 commits) ARM: exynos: don't run exynos4 l2x0 setup on other platforms ARM: exynos: Fix "allmodconfig" build errors in mcpm and hotplug ARM: EXYNOS: mcpm rename the power_down_finish ARM: EXYNOS: Enable mcpm for dual-cluster exynos5800 SoC ARM: EXYNOS: Enable multi-platform build support ARM: EXYNOS: Consolidate Kconfig entries ARM: EXYNOS: Add support for EXYNOS5410 SoC ARM: EXYNOS: Support secondary CPU boot of Exynos3250 ARM: EXYNOS: Add Exynos3250 SoC ID ARM: EXYNOS: Add 5800 SoC support ARM: EXYNOS: initial board support for exynos5260 SoC clk: exynos5410: register clocks using common clock framework ARM: debug: qcom: add UART addresses to Kconfig help for APQ8084 ARM: sunxi: allow building without reset controller Documentation: devicetree: arm: sort enable-method entries ARM: rockchip: convert smp bringup to CPU_METHOD_OF_DECLARE clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks ARM: dts: axxia: Add reset controller power: reset: Add Axxia system reset driver ARM: axxia: Adding defconfig for AXM55xx ...
161 lines
3.7 KiB
C
161 lines
3.7 KiB
C
/*
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* ID and revision information for mvebu SoCs
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*
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* Copyright (C) 2014 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* All the mvebu SoCs have information related to their variant and
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* revision that can be read from the PCI control register. This is
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* done before the PCI initialization to avoid any conflict. Once the
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* ID and revision are retrieved, the mapping is freed.
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*/
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#define pr_fmt(fmt) "mvebu-soc-id: " fmt
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#include <linux/clk.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/sys_soc.h>
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#include "mvebu-soc-id.h"
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#define PCIE_DEV_ID_OFF 0x0
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#define PCIE_DEV_REV_OFF 0x8
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#define SOC_ID_MASK 0xFFFF0000
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#define SOC_REV_MASK 0xFF
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static u32 soc_dev_id;
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static u32 soc_rev;
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static bool is_id_valid;
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static const struct of_device_id mvebu_pcie_of_match_table[] = {
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{ .compatible = "marvell,armada-xp-pcie", },
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{ .compatible = "marvell,armada-370-pcie", },
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{ .compatible = "marvell,kirkwood-pcie" },
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{},
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};
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int mvebu_get_soc_id(u32 *dev, u32 *rev)
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{
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if (is_id_valid) {
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*dev = soc_dev_id;
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*rev = soc_rev;
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return 0;
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} else
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return -1;
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}
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static int __init mvebu_soc_id_init(void)
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{
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struct device_node *np;
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int ret = 0;
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void __iomem *pci_base;
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struct clk *clk;
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struct device_node *child;
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np = of_find_matching_node(NULL, mvebu_pcie_of_match_table);
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if (!np)
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return ret;
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/*
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* ID and revision are available from any port, so we
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* just pick the first one
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*/
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child = of_get_next_child(np, NULL);
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if (child == NULL) {
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pr_err("cannot get pci node\n");
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ret = -ENOMEM;
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goto clk_err;
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}
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clk = of_clk_get_by_name(child, NULL);
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if (IS_ERR(clk)) {
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pr_err("cannot get clock\n");
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ret = -ENOMEM;
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goto clk_err;
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("cannot enable clock\n");
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goto clk_err;
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}
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pci_base = of_iomap(child, 0);
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if (pci_base == NULL) {
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pr_err("cannot map registers\n");
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ret = -ENOMEM;
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goto res_ioremap;
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}
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/* SoC ID */
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soc_dev_id = readl(pci_base + PCIE_DEV_ID_OFF) >> 16;
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/* SoC revision */
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soc_rev = readl(pci_base + PCIE_DEV_REV_OFF) & SOC_REV_MASK;
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is_id_valid = true;
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pr_info("MVEBU SoC ID=0x%X, Rev=0x%X\n", soc_dev_id, soc_rev);
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iounmap(pci_base);
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res_ioremap:
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/*
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* If the PCIe unit is actually enabled and we have PCI
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* support in the kernel, we intentionally do not release the
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* reference to the clock. We want to keep it running since
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* the bootloader does some PCIe link configuration that the
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* kernel is for now unable to do, and gating the clock would
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* make us loose this precious configuration.
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*/
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if (!of_device_is_available(child) || !IS_ENABLED(CONFIG_PCI_MVEBU)) {
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clk_disable_unprepare(clk);
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clk_put(clk);
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}
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clk_err:
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of_node_put(child);
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of_node_put(np);
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return ret;
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}
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early_initcall(mvebu_soc_id_init);
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static int __init mvebu_soc_device(void)
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{
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struct soc_device_attribute *soc_dev_attr;
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struct soc_device *soc_dev;
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/* Also protects against running on non-mvebu systems */
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if (!is_id_valid)
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return 0;
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soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
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if (!soc_dev_attr)
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return -ENOMEM;
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soc_dev_attr->family = kasprintf(GFP_KERNEL, "Marvell");
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soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X", soc_rev);
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soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%X", soc_dev_id);
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soc_dev = soc_device_register(soc_dev_attr);
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if (IS_ERR(soc_dev)) {
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kfree(soc_dev_attr->family);
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kfree(soc_dev_attr->revision);
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kfree(soc_dev_attr->soc_id);
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kfree(soc_dev_attr);
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}
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return 0;
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}
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postcore_initcall(mvebu_soc_device);
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