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![Peter Korsgaard](/assets/img/avatar_default.png)
Error out on transfer length != multiple of bytes per word with -EINVAL. Fixes a buffer overrun crash if length < bytes per word. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
712 lines
17 KiB
C
712 lines
17 KiB
C
/*
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* MPC83xx SPI controller driver.
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*
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* Maintainer: Kumar Gala
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*
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* Copyright (C) 2006 Polycom, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/completion.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/platform_device.h>
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#include <linux/fsl_devices.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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/* SPI Controller registers */
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struct mpc83xx_spi_reg {
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u8 res1[0x20];
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__be32 mode;
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__be32 event;
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__be32 mask;
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__be32 command;
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__be32 transmit;
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__be32 receive;
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};
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/* SPI Controller mode register definitions */
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#define SPMODE_LOOP (1 << 30)
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#define SPMODE_CI_INACTIVEHIGH (1 << 29)
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#define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
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#define SPMODE_DIV16 (1 << 27)
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#define SPMODE_REV (1 << 26)
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#define SPMODE_MS (1 << 25)
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#define SPMODE_ENABLE (1 << 24)
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#define SPMODE_LEN(x) ((x) << 20)
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#define SPMODE_PM(x) ((x) << 16)
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#define SPMODE_OP (1 << 14)
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#define SPMODE_CG(x) ((x) << 7)
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/*
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* Default for SPI Mode:
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* SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
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*/
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#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
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SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
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/* SPIE register values */
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#define SPIE_NE 0x00000200 /* Not empty */
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#define SPIE_NF 0x00000100 /* Not full */
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/* SPIM register values */
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#define SPIM_NE 0x00000200 /* Not empty */
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#define SPIM_NF 0x00000100 /* Not full */
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/* SPI Controller driver's private data. */
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struct mpc83xx_spi {
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struct mpc83xx_spi_reg __iomem *base;
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/* rx & tx bufs from the spi_transfer */
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const void *tx;
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void *rx;
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/* functions to deal with different sized buffers */
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void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
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u32(*get_tx) (struct mpc83xx_spi *);
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unsigned int count;
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int irq;
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unsigned nsecs; /* (clock cycle time)/2 */
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u32 spibrg; /* SPIBRG input clock */
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u32 rx_shift; /* RX data reg shift when in qe mode */
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u32 tx_shift; /* TX data reg shift when in qe mode */
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bool qe_mode;
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void (*activate_cs) (u8 cs, u8 polarity);
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void (*deactivate_cs) (u8 cs, u8 polarity);
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u8 busy;
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struct workqueue_struct *workqueue;
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struct work_struct work;
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struct list_head queue;
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spinlock_t lock;
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struct completion done;
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};
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struct spi_mpc83xx_cs {
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/* functions to deal with different sized buffers */
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void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
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u32 (*get_tx) (struct mpc83xx_spi *);
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u32 rx_shift; /* RX data reg shift when in qe mode */
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u32 tx_shift; /* TX data reg shift when in qe mode */
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u32 hw_mode; /* Holds HW mode register settings */
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};
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static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
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{
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out_be32(reg, val);
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}
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static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
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{
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return in_be32(reg);
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}
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#define MPC83XX_SPI_RX_BUF(type) \
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void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
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{ \
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type * rx = mpc83xx_spi->rx; \
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*rx++ = (type)(data >> mpc83xx_spi->rx_shift); \
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mpc83xx_spi->rx = rx; \
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}
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#define MPC83XX_SPI_TX_BUF(type) \
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u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \
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{ \
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u32 data; \
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const type * tx = mpc83xx_spi->tx; \
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if (!tx) \
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return 0; \
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data = *tx++ << mpc83xx_spi->tx_shift; \
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mpc83xx_spi->tx = tx; \
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return data; \
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}
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MPC83XX_SPI_RX_BUF(u8)
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MPC83XX_SPI_RX_BUF(u16)
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MPC83XX_SPI_RX_BUF(u32)
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MPC83XX_SPI_TX_BUF(u8)
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MPC83XX_SPI_TX_BUF(u16)
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MPC83XX_SPI_TX_BUF(u32)
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static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
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{
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struct mpc83xx_spi *mpc83xx_spi;
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u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
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struct spi_mpc83xx_cs *cs = spi->controller_state;
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mpc83xx_spi = spi_master_get_devdata(spi->master);
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if (value == BITBANG_CS_INACTIVE) {
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if (mpc83xx_spi->deactivate_cs)
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mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
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}
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if (value == BITBANG_CS_ACTIVE) {
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u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
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mpc83xx_spi->rx_shift = cs->rx_shift;
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mpc83xx_spi->tx_shift = cs->tx_shift;
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mpc83xx_spi->get_rx = cs->get_rx;
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mpc83xx_spi->get_tx = cs->get_tx;
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if (cs->hw_mode != regval) {
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unsigned long flags;
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void *tmp_ptr = &mpc83xx_spi->base->mode;
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regval = cs->hw_mode;
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/* Turn off IRQs locally to minimize time that
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* SPI is disabled
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*/
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local_irq_save(flags);
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/* Turn off SPI unit prior changing mode */
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mpc83xx_spi_write_reg(tmp_ptr, regval & ~SPMODE_ENABLE);
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mpc83xx_spi_write_reg(tmp_ptr, regval);
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local_irq_restore(flags);
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}
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if (mpc83xx_spi->activate_cs)
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mpc83xx_spi->activate_cs(spi->chip_select, pol);
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}
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}
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static
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int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
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{
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struct mpc83xx_spi *mpc83xx_spi;
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u32 regval;
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u8 bits_per_word, pm;
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u32 hz;
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struct spi_mpc83xx_cs *cs = spi->controller_state;
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mpc83xx_spi = spi_master_get_devdata(spi->master);
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if (t) {
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bits_per_word = t->bits_per_word;
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hz = t->speed_hz;
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} else {
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bits_per_word = 0;
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hz = 0;
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}
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/* spi_transfer level calls that work per-word */
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if (!bits_per_word)
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bits_per_word = spi->bits_per_word;
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/* Make sure its a bit width we support [4..16, 32] */
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if ((bits_per_word < 4)
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|| ((bits_per_word > 16) && (bits_per_word != 32)))
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return -EINVAL;
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if (!hz)
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hz = spi->max_speed_hz;
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cs->rx_shift = 0;
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cs->tx_shift = 0;
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if (bits_per_word <= 8) {
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cs->get_rx = mpc83xx_spi_rx_buf_u8;
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cs->get_tx = mpc83xx_spi_tx_buf_u8;
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if (mpc83xx_spi->qe_mode) {
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cs->rx_shift = 16;
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cs->tx_shift = 24;
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}
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} else if (bits_per_word <= 16) {
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cs->get_rx = mpc83xx_spi_rx_buf_u16;
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cs->get_tx = mpc83xx_spi_tx_buf_u16;
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if (mpc83xx_spi->qe_mode) {
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cs->rx_shift = 16;
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cs->tx_shift = 16;
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}
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} else if (bits_per_word <= 32) {
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cs->get_rx = mpc83xx_spi_rx_buf_u32;
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cs->get_tx = mpc83xx_spi_tx_buf_u32;
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} else
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return -EINVAL;
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if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
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cs->tx_shift = 0;
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if (bits_per_word <= 8)
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cs->rx_shift = 8;
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else
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cs->rx_shift = 0;
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}
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mpc83xx_spi->rx_shift = cs->rx_shift;
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mpc83xx_spi->tx_shift = cs->tx_shift;
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mpc83xx_spi->get_rx = cs->get_rx;
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mpc83xx_spi->get_tx = cs->get_tx;
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if (bits_per_word == 32)
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bits_per_word = 0;
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else
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bits_per_word = bits_per_word - 1;
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/* mask out bits we are going to set */
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cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
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| SPMODE_PM(0xF));
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cs->hw_mode |= SPMODE_LEN(bits_per_word);
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if ((mpc83xx_spi->spibrg / hz) > 64) {
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cs->hw_mode |= SPMODE_DIV16;
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pm = mpc83xx_spi->spibrg / (hz * 64);
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if (pm > 16) {
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dev_err(&spi->dev, "Requested speed is too "
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"low: %d Hz. Will use %d Hz instead.\n",
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hz, mpc83xx_spi->spibrg / 1024);
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pm = 16;
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}
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} else
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pm = mpc83xx_spi->spibrg / (hz * 4);
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if (pm)
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pm--;
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cs->hw_mode |= SPMODE_PM(pm);
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regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
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if (cs->hw_mode != regval) {
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unsigned long flags;
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void *tmp_ptr = &mpc83xx_spi->base->mode;
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regval = cs->hw_mode;
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/* Turn off IRQs locally to minimize time
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* that SPI is disabled
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*/
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local_irq_save(flags);
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/* Turn off SPI unit prior changing mode */
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mpc83xx_spi_write_reg(tmp_ptr, regval & ~SPMODE_ENABLE);
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mpc83xx_spi_write_reg(tmp_ptr, regval);
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local_irq_restore(flags);
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}
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return 0;
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}
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static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
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{
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struct mpc83xx_spi *mpc83xx_spi;
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u32 word, len, bits_per_word;
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mpc83xx_spi = spi_master_get_devdata(spi->master);
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mpc83xx_spi->tx = t->tx_buf;
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mpc83xx_spi->rx = t->rx_buf;
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bits_per_word = spi->bits_per_word;
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if (t->bits_per_word)
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bits_per_word = t->bits_per_word;
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len = t->len;
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if (bits_per_word > 8) {
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/* invalid length? */
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if (len & 1)
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return -EINVAL;
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len /= 2;
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}
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if (bits_per_word > 16) {
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/* invalid length? */
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if (len & 1)
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return -EINVAL;
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len /= 2;
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}
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mpc83xx_spi->count = len;
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INIT_COMPLETION(mpc83xx_spi->done);
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/* enable rx ints */
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mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
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/* transmit word */
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word = mpc83xx_spi->get_tx(mpc83xx_spi);
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mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
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wait_for_completion(&mpc83xx_spi->done);
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/* disable rx ints */
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mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
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return mpc83xx_spi->count;
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}
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static void mpc83xx_spi_work(struct work_struct *work)
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{
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struct mpc83xx_spi *mpc83xx_spi =
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container_of(work, struct mpc83xx_spi, work);
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spin_lock_irq(&mpc83xx_spi->lock);
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mpc83xx_spi->busy = 1;
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while (!list_empty(&mpc83xx_spi->queue)) {
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struct spi_message *m;
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struct spi_device *spi;
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struct spi_transfer *t = NULL;
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unsigned cs_change;
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int status, nsecs = 50;
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m = container_of(mpc83xx_spi->queue.next,
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struct spi_message, queue);
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list_del_init(&m->queue);
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spin_unlock_irq(&mpc83xx_spi->lock);
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spi = m->spi;
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cs_change = 1;
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status = 0;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (t->bits_per_word || t->speed_hz) {
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/* Don't allow changes if CS is active */
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status = -EINVAL;
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if (cs_change)
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status = mpc83xx_spi_setup_transfer(spi, t);
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if (status < 0)
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break;
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}
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if (cs_change)
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mpc83xx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
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cs_change = t->cs_change;
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if (t->len)
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status = mpc83xx_spi_bufs(spi, t);
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if (status) {
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status = -EMSGSIZE;
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break;
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}
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m->actual_length += t->len;
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if (t->delay_usecs)
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udelay(t->delay_usecs);
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if (cs_change) {
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ndelay(nsecs);
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mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
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ndelay(nsecs);
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}
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}
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m->status = status;
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m->complete(m->context);
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if (status || !cs_change) {
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ndelay(nsecs);
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mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
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}
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mpc83xx_spi_setup_transfer(spi, NULL);
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spin_lock_irq(&mpc83xx_spi->lock);
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}
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mpc83xx_spi->busy = 0;
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spin_unlock_irq(&mpc83xx_spi->lock);
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}
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/* the spi->mode bits understood by this driver: */
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#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
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| SPI_LSB_FIRST | SPI_LOOP)
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static int mpc83xx_spi_setup(struct spi_device *spi)
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{
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struct mpc83xx_spi *mpc83xx_spi;
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int retval;
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u32 hw_mode;
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struct spi_mpc83xx_cs *cs = spi->controller_state;
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if (spi->mode & ~MODEBITS) {
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dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
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spi->mode & ~MODEBITS);
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return -EINVAL;
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}
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if (!spi->max_speed_hz)
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return -EINVAL;
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if (!cs) {
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cs = kzalloc(sizeof *cs, GFP_KERNEL);
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if (!cs)
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return -ENOMEM;
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spi->controller_state = cs;
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}
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mpc83xx_spi = spi_master_get_devdata(spi->master);
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if (!spi->bits_per_word)
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spi->bits_per_word = 8;
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hw_mode = cs->hw_mode; /* Save orginal settings */
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cs->hw_mode = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
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/* mask out bits we are going to set */
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cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
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| SPMODE_REV | SPMODE_LOOP);
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if (spi->mode & SPI_CPHA)
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cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
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if (spi->mode & SPI_CPOL)
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cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
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if (!(spi->mode & SPI_LSB_FIRST))
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cs->hw_mode |= SPMODE_REV;
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if (spi->mode & SPI_LOOP)
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cs->hw_mode |= SPMODE_LOOP;
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retval = mpc83xx_spi_setup_transfer(spi, NULL);
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if (retval < 0) {
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cs->hw_mode = hw_mode; /* Restore settings */
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return retval;
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}
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dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u Hz\n",
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__func__, spi->mode & (SPI_CPOL | SPI_CPHA),
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spi->bits_per_word, spi->max_speed_hz);
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#if 0 /* Don't think this is needed */
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/* NOTE we _need_ to call chipselect() early, ideally with adapter
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* setup, unless the hardware defaults cooperate to avoid confusion
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* between normal (active low) and inverted chipselects.
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*/
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|
|
/* deselect chip (low or high) */
|
|
spin_lock(&mpc83xx_spi->lock);
|
|
if (!mpc83xx_spi->busy)
|
|
mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
|
|
spin_unlock(&mpc83xx_spi->lock);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
|
|
{
|
|
struct mpc83xx_spi *mpc83xx_spi = context_data;
|
|
u32 event;
|
|
irqreturn_t ret = IRQ_NONE;
|
|
|
|
/* Get interrupt events(tx/rx) */
|
|
event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
|
|
|
|
/* We need handle RX first */
|
|
if (event & SPIE_NE) {
|
|
u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
|
|
|
|
if (mpc83xx_spi->rx)
|
|
mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
|
|
|
|
ret = IRQ_HANDLED;
|
|
}
|
|
|
|
if ((event & SPIE_NF) == 0)
|
|
/* spin until TX is done */
|
|
while (((event =
|
|
mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
|
|
SPIE_NF) == 0)
|
|
cpu_relax();
|
|
|
|
mpc83xx_spi->count -= 1;
|
|
if (mpc83xx_spi->count) {
|
|
u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
|
|
mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
|
|
} else {
|
|
complete(&mpc83xx_spi->done);
|
|
}
|
|
|
|
/* Clear the events */
|
|
mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
|
|
|
|
return ret;
|
|
}
|
|
static int mpc83xx_spi_transfer(struct spi_device *spi,
|
|
struct spi_message *m)
|
|
{
|
|
struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
|
|
unsigned long flags;
|
|
|
|
m->actual_length = 0;
|
|
m->status = -EINPROGRESS;
|
|
|
|
spin_lock_irqsave(&mpc83xx_spi->lock, flags);
|
|
list_add_tail(&m->queue, &mpc83xx_spi->queue);
|
|
queue_work(mpc83xx_spi->workqueue, &mpc83xx_spi->work);
|
|
spin_unlock_irqrestore(&mpc83xx_spi->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static void mpc83xx_spi_cleanup(struct spi_device *spi)
|
|
{
|
|
kfree(spi->controller_state);
|
|
}
|
|
|
|
static int __init mpc83xx_spi_probe(struct platform_device *dev)
|
|
{
|
|
struct spi_master *master;
|
|
struct mpc83xx_spi *mpc83xx_spi;
|
|
struct fsl_spi_platform_data *pdata;
|
|
struct resource *r;
|
|
u32 regval;
|
|
int ret = 0;
|
|
|
|
/* Get resources(memory, IRQ) associated with the device */
|
|
master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
|
|
|
|
if (master == NULL) {
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
platform_set_drvdata(dev, master);
|
|
pdata = dev->dev.platform_data;
|
|
|
|
if (pdata == NULL) {
|
|
ret = -ENODEV;
|
|
goto free_master;
|
|
}
|
|
|
|
r = platform_get_resource(dev, IORESOURCE_MEM, 0);
|
|
if (r == NULL) {
|
|
ret = -ENODEV;
|
|
goto free_master;
|
|
}
|
|
master->setup = mpc83xx_spi_setup;
|
|
master->transfer = mpc83xx_spi_transfer;
|
|
master->cleanup = mpc83xx_spi_cleanup;
|
|
|
|
mpc83xx_spi = spi_master_get_devdata(master);
|
|
mpc83xx_spi->activate_cs = pdata->activate_cs;
|
|
mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
|
|
mpc83xx_spi->qe_mode = pdata->qe_mode;
|
|
mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
|
|
mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
|
|
mpc83xx_spi->spibrg = pdata->sysclk;
|
|
|
|
mpc83xx_spi->rx_shift = 0;
|
|
mpc83xx_spi->tx_shift = 0;
|
|
if (mpc83xx_spi->qe_mode) {
|
|
mpc83xx_spi->rx_shift = 16;
|
|
mpc83xx_spi->tx_shift = 24;
|
|
}
|
|
|
|
init_completion(&mpc83xx_spi->done);
|
|
|
|
mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
|
|
if (mpc83xx_spi->base == NULL) {
|
|
ret = -ENOMEM;
|
|
goto put_master;
|
|
}
|
|
|
|
mpc83xx_spi->irq = platform_get_irq(dev, 0);
|
|
|
|
if (mpc83xx_spi->irq < 0) {
|
|
ret = -ENXIO;
|
|
goto unmap_io;
|
|
}
|
|
|
|
/* Register for SPI Interrupt */
|
|
ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
|
|
0, "mpc83xx_spi", mpc83xx_spi);
|
|
|
|
if (ret != 0)
|
|
goto unmap_io;
|
|
|
|
master->bus_num = pdata->bus_num;
|
|
master->num_chipselect = pdata->max_chipselect;
|
|
|
|
/* SPI controller initializations */
|
|
mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
|
|
mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
|
|
mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
|
|
mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
|
|
|
|
/* Enable SPI interface */
|
|
regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
|
|
if (pdata->qe_mode)
|
|
regval |= SPMODE_OP;
|
|
|
|
mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
|
|
spin_lock_init(&mpc83xx_spi->lock);
|
|
init_completion(&mpc83xx_spi->done);
|
|
INIT_WORK(&mpc83xx_spi->work, mpc83xx_spi_work);
|
|
INIT_LIST_HEAD(&mpc83xx_spi->queue);
|
|
|
|
mpc83xx_spi->workqueue = create_singlethread_workqueue(
|
|
master->dev.parent->bus_id);
|
|
if (mpc83xx_spi->workqueue == NULL) {
|
|
ret = -EBUSY;
|
|
goto free_irq;
|
|
}
|
|
|
|
ret = spi_register_master(master);
|
|
if (ret < 0)
|
|
goto unreg_master;
|
|
|
|
printk(KERN_INFO
|
|
"%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
|
|
dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq);
|
|
|
|
return ret;
|
|
|
|
unreg_master:
|
|
destroy_workqueue(mpc83xx_spi->workqueue);
|
|
free_irq:
|
|
free_irq(mpc83xx_spi->irq, mpc83xx_spi);
|
|
unmap_io:
|
|
iounmap(mpc83xx_spi->base);
|
|
put_master:
|
|
spi_master_put(master);
|
|
free_master:
|
|
kfree(master);
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
static int __exit mpc83xx_spi_remove(struct platform_device *dev)
|
|
{
|
|
struct mpc83xx_spi *mpc83xx_spi;
|
|
struct spi_master *master;
|
|
|
|
master = platform_get_drvdata(dev);
|
|
mpc83xx_spi = spi_master_get_devdata(master);
|
|
|
|
flush_workqueue(mpc83xx_spi->workqueue);
|
|
destroy_workqueue(mpc83xx_spi->workqueue);
|
|
spi_unregister_master(master);
|
|
|
|
free_irq(mpc83xx_spi->irq, mpc83xx_spi);
|
|
iounmap(mpc83xx_spi->base);
|
|
|
|
return 0;
|
|
}
|
|
|
|
MODULE_ALIAS("platform:mpc83xx_spi");
|
|
static struct platform_driver mpc83xx_spi_driver = {
|
|
.remove = __exit_p(mpc83xx_spi_remove),
|
|
.driver = {
|
|
.name = "mpc83xx_spi",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init mpc83xx_spi_init(void)
|
|
{
|
|
return platform_driver_probe(&mpc83xx_spi_driver, mpc83xx_spi_probe);
|
|
}
|
|
|
|
static void __exit mpc83xx_spi_exit(void)
|
|
{
|
|
platform_driver_unregister(&mpc83xx_spi_driver);
|
|
}
|
|
|
|
module_init(mpc83xx_spi_init);
|
|
module_exit(mpc83xx_spi_exit);
|
|
|
|
MODULE_AUTHOR("Kumar Gala");
|
|
MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
|
|
MODULE_LICENSE("GPL");
|