mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-15 23:25:07 +00:00
876611c493
This patch implements the basic functions of the BMC chip for some Intel FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the Intel MAX 10 CPLD. This BMC chip is connected to the FPGA by a SPI bus. To provide direct register access from the FPGA, the "SPI slave to Avalon Master Bridge" (spi-avmm) IP is integrated in the chip. It converts encoded streams of bytes from the host to the internal register read/write on the Avalon bus. So This driver uses the regmap-spi-avmm for register accessing. Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
15 lines
445 B
Text
15 lines
445 B
Text
What: /sys/bus/spi/devices/.../bmc_version
|
|
Date: June 2020
|
|
KernelVersion: 5.10
|
|
Contact: Xu Yilun <yilun.xu@intel.com>
|
|
Description: Read only. Returns the hardware build version of Intel
|
|
MAX10 BMC chip.
|
|
Format: "0x%x".
|
|
|
|
What: /sys/bus/spi/devices/.../bmcfw_version
|
|
Date: June 2020
|
|
KernelVersion: 5.10
|
|
Contact: Xu Yilun <yilun.xu@intel.com>
|
|
Description: Read only. Returns the firmware version of Intel MAX10
|
|
BMC chip.
|
|
Format: "0x%x".
|