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eb33cd9116
On CN10K platform transmit/receive buffer alloc and free from/to hardware had changed to support burst operation. Whereas pervious silicon's only support single buffer free at a time. To Support the same firmware allocates a DRAM region for each PF/VF for storing LMTLINES. These LMTLINES are used to send CPT commands to HW. PF/VF LMTST region is accessed via BAR4. PFs LMTST region is followed by its VFs mbox memory. The size of region varies from 2KB to 256KB based on number of LMTLINES configured. This patch adds support for mapping of PF/VF LMTST region. Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
11 lines
461 B
Makefile
11 lines
461 B
Makefile
# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_CRYPTO_DEV_OCTEONTX2_CPT) += rvu_cptpf.o rvu_cptvf.o
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rvu_cptpf-objs := otx2_cptpf_main.o otx2_cptpf_mbox.o \
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otx2_cpt_mbox_common.o otx2_cptpf_ucode.o otx2_cptlf.o \
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cn10k_cpt.o
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rvu_cptvf-objs := otx2_cptvf_main.o otx2_cptvf_mbox.o otx2_cptlf.o \
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otx2_cpt_mbox_common.o otx2_cptvf_reqmgr.o \
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otx2_cptvf_algs.o cn10k_cpt.o
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ccflags-y += -I$(srctree)/drivers/net/ethernet/marvell/octeontx2/af
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