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synced 2024-08-26 19:00:25 +00:00
![Linus Torvalds](/assets/img/avatar_default.png)
- New driver for the Qualcomm TLMM pin controller and its msm8x74 subdriver. - New driver for the Broadcom Capri BCM281xx SoC. - New subdriver for the imx25 pin controller. - New subdriver for the Tegra124 pin controller. - Lock GPIO lines as IRQs for select combined pin control and GPIO drivers for baytrail and sirf. - Some semi-big refactorings and extenstions to the sirf driver. - Lots of patching, cleanup and fixing in the Renesas "PFC" driver and associated subdrivers as usual. It is settling down a little bit now it seems. - Minor fixes and incremental updates here and there as usual. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJS3mvwAAoJEEEQszewGV1zc3wP/RYjFaS4WGXX/QnvXGlTwpyb 3IIQM4l507ds97ipjip9OO31od8HqkWw4lREwKvRdtqItZJiSzG3oYwn+ro+X2E5 tif0kDxae1tFWieVjA2+zuvjZ76ve8FsVUuUTY7qdd4jdD3OO6P9BgDT0QqwN1Uh QToszugQzeOqJARn/DKHg2hkBlg0NorasskCvy6qALbXkWIpLm0U4di2HmGgvV2e 5YqRCA8uAf48fE6Q93PQNYQU7Zux1Lyr59y0Wl/pnfKKvi1qG2KPnHDJhMmUbxJk tWi2VcB1Msrhccv+o0onNMfILG0xInmss3NELTTJJEhSjDvaETkng9fCbw4XDaKY KLQ7aRjodbGlvdAONqzZR6e0Ra+piGKDdm94+hvOn0BS1SVfjVA7d6AaeTdR6g+6 GD+EVqzczAtla8g1xwNKp69SDN1I3yddMQzjQProSE/eGaQYN6aJW+2hDpD3SoOD uezFyktzehCIJ5WOIcth8RapN7p33w7bbDOuGVESCesF4NcaUqF+19ukAN9kzVhd 6oksU1RsxLUdBg/zO7Dwyuhx0XzOuBvrP3EADU37MpnTyCGz4ko4vH0T7JHaA5Oe lN9otYBZT0p/kYUEdINjF3foc7f2yc8adC5kDUB9p/zdzyPIwCijGGD6shJGr11/ 7SQ8DvyJZeq3lSNs8+RG =ol2E -----END PGP SIGNATURE----- Merge tag 'pinctrl-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull bulk pin control changes from Linus Walleij: "This has been queued and tested for a while. Lots of action here, like in the GPIO tree, embedded stuff like this is really hot now it seems. Details in the signed tag. I'm especially happy about the Qualcomm driver as it is used in such a huge subset of mobile handsets out there, and these platforms in general need better upstream support - New driver for the Qualcomm TLMM pin controller and its msm8x74 subdriver. - New driver for the Broadcom Capri BCM281xx SoC. - New subdriver for the imx25 pin controller. - New subdriver for the Tegra124 pin controller. - Lock GPIO lines as IRQs for select combined pin control and GPIO drivers for baytrail and sirf. - Some semi-big refactorings and extenstions to the sirf driver. - Lots of patching, cleanup and fixing in the Renesas "PFC" driver and associated subdrivers as usual. It is settling down a little bit now it seems. - Minor fixes and incremental updates here and there as usual" * tag 'pinctrl-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits) pinctrl: sunxi: Honor GPIO output initial vaules pinctrl: capri: add dependency on OF ARM: bcm11351: Enable pinctrl for Broadcom Capri SoCs ARM: pinctrl: Add Broadcom Capri pinctrl driver pinctrl: Add pinctrl binding for Broadcom Capri SoCs pinctrl: Add void * to pinctrl_pin_desc pinctrl: st: Fix a typo in probe pinctrl: Fix some typos and grammar issues in the documentation pinctrl: sirf: lock IRQs when starting them pinctrl: sirf: put gpio interrupt pin into input status automatically pinctrl: sirf: use only one irq_domain for the whole device node pinctrl: single: fix infinite loop caused by bad mask pinctrl: single: fix pcs_disable with bits_per_mux pinctrl: single: fix DT bindings documentation pinctrl: as3722: Set pin to output mode for some function pinctrl: sirf: add pin group for USP0 with only RX or TX frame sync pinctrl: sirf: fix the pins of sdmmc5 connected with TriG pinctrl: sirf: add lost usp1_uart_nostreamctrl group for atlas6 pinctrl: sunxi: Add Allwinner A20 clock output pin functions pinctrl/lantiq: fix typo ...
934 lines
23 KiB
C
934 lines
23 KiB
C
/*
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* Allwinner A1X SoCs pinctrl driver.
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*
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* Copyright (C) 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/gpio.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "core.h"
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#include "pinctrl-sunxi.h"
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#include "pinctrl-sunxi-pins.h"
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static struct sunxi_pinctrl_group *
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sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
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{
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int i;
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for (i = 0; i < pctl->ngroups; i++) {
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struct sunxi_pinctrl_group *grp = pctl->groups + i;
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if (!strcmp(grp->name, group))
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return grp;
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}
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return NULL;
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}
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static struct sunxi_pinctrl_function *
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sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
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const char *name)
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{
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struct sunxi_pinctrl_function *func = pctl->functions;
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int i;
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for (i = 0; i < pctl->nfunctions; i++) {
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if (!func[i].name)
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break;
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if (!strcmp(func[i].name, name))
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return func + i;
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}
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return NULL;
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}
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static struct sunxi_desc_function *
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sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
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const char *pin_name,
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const char *func_name)
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{
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int i;
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for (i = 0; i < pctl->desc->npins; i++) {
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const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
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if (!strcmp(pin->pin.name, pin_name)) {
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struct sunxi_desc_function *func = pin->functions;
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while (func->name) {
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if (!strcmp(func->name, func_name))
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return func;
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func++;
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}
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}
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}
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return NULL;
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}
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static struct sunxi_desc_function *
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sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
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const u16 pin_num,
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const char *func_name)
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{
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int i;
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for (i = 0; i < pctl->desc->npins; i++) {
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const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
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if (pin->pin.number == pin_num) {
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struct sunxi_desc_function *func = pin->functions;
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while (func->name) {
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if (!strcmp(func->name, func_name))
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return func;
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func++;
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}
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}
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}
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return NULL;
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}
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static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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return pctl->ngroups;
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}
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static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
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unsigned group)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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return pctl->groups[group].name;
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}
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static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned group,
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const unsigned **pins,
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unsigned *num_pins)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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*pins = (unsigned *)&pctl->groups[group].pin;
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*num_pins = 1;
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return 0;
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}
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static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
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struct device_node *node,
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struct pinctrl_map **map,
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unsigned *num_maps)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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unsigned long *pinconfig;
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struct property *prop;
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const char *function;
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const char *group;
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int ret, nmaps, i = 0;
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u32 val;
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*map = NULL;
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*num_maps = 0;
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ret = of_property_read_string(node, "allwinner,function", &function);
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if (ret) {
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dev_err(pctl->dev,
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"missing allwinner,function property in node %s\n",
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node->name);
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return -EINVAL;
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}
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nmaps = of_property_count_strings(node, "allwinner,pins") * 2;
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if (nmaps < 0) {
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dev_err(pctl->dev,
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"missing allwinner,pins property in node %s\n",
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node->name);
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return -EINVAL;
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}
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*map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
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if (!*map)
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return -ENOMEM;
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of_property_for_each_string(node, "allwinner,pins", prop, group) {
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struct sunxi_pinctrl_group *grp =
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sunxi_pinctrl_find_group_by_name(pctl, group);
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int j = 0, configlen = 0;
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if (!grp) {
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dev_err(pctl->dev, "unknown pin %s", group);
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continue;
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}
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if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
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grp->name,
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function)) {
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dev_err(pctl->dev, "unsupported function %s on pin %s",
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function, group);
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continue;
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}
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(*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
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(*map)[i].data.mux.group = group;
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(*map)[i].data.mux.function = function;
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i++;
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(*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
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(*map)[i].data.configs.group_or_pin = group;
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if (of_find_property(node, "allwinner,drive", NULL))
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configlen++;
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if (of_find_property(node, "allwinner,pull", NULL))
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configlen++;
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pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
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if (!of_property_read_u32(node, "allwinner,drive", &val)) {
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u16 strength = (val + 1) * 10;
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pinconfig[j++] =
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pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
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strength);
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}
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if (!of_property_read_u32(node, "allwinner,pull", &val)) {
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enum pin_config_param pull = PIN_CONFIG_END;
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if (val == 1)
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pull = PIN_CONFIG_BIAS_PULL_UP;
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else if (val == 2)
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pull = PIN_CONFIG_BIAS_PULL_DOWN;
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pinconfig[j++] = pinconf_to_config_packed(pull, 0);
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}
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(*map)[i].data.configs.configs = pinconfig;
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(*map)[i].data.configs.num_configs = configlen;
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i++;
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}
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*num_maps = nmaps;
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return 0;
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}
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static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
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struct pinctrl_map *map,
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unsigned num_maps)
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{
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int i;
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for (i = 0; i < num_maps; i++) {
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if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
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kfree(map[i].data.configs.configs);
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}
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kfree(map);
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}
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static const struct pinctrl_ops sunxi_pctrl_ops = {
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.dt_node_to_map = sunxi_pctrl_dt_node_to_map,
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.dt_free_map = sunxi_pctrl_dt_free_map,
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.get_groups_count = sunxi_pctrl_get_groups_count,
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.get_group_name = sunxi_pctrl_get_group_name,
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.get_group_pins = sunxi_pctrl_get_group_pins,
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};
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static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
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unsigned group,
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unsigned long *config)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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*config = pctl->groups[group].config;
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return 0;
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}
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static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
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unsigned group,
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unsigned long *configs,
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unsigned num_configs)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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struct sunxi_pinctrl_group *g = &pctl->groups[group];
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unsigned long flags;
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u32 val, mask;
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u16 strength;
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u8 dlevel;
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int i;
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spin_lock_irqsave(&pctl->lock, flags);
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for (i = 0; i < num_configs; i++) {
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switch (pinconf_to_config_param(configs[i])) {
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case PIN_CONFIG_DRIVE_STRENGTH:
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strength = pinconf_to_config_argument(configs[i]);
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if (strength > 40) {
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spin_unlock_irqrestore(&pctl->lock, flags);
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return -EINVAL;
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}
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/*
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* We convert from mA to what the register expects:
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* 0: 10mA
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* 1: 20mA
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* 2: 30mA
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* 3: 40mA
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*/
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dlevel = strength / 10 - 1;
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val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
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mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
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writel((val & ~mask)
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| dlevel << sunxi_dlevel_offset(g->pin),
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pctl->membase + sunxi_dlevel_reg(g->pin));
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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val = readl(pctl->membase + sunxi_pull_reg(g->pin));
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mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
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writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
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pctl->membase + sunxi_pull_reg(g->pin));
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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val = readl(pctl->membase + sunxi_pull_reg(g->pin));
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mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
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writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
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pctl->membase + sunxi_pull_reg(g->pin));
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break;
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default:
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break;
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}
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/* cache the config value */
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g->config = configs[i];
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} /* for each config */
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spin_unlock_irqrestore(&pctl->lock, flags);
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return 0;
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}
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static const struct pinconf_ops sunxi_pconf_ops = {
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.pin_config_group_get = sunxi_pconf_group_get,
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.pin_config_group_set = sunxi_pconf_group_set,
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};
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static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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return pctl->nfunctions;
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}
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static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
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unsigned function)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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return pctl->functions[function].name;
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}
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static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
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unsigned function,
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const char * const **groups,
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unsigned * const num_groups)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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*groups = pctl->functions[function].groups;
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*num_groups = pctl->functions[function].ngroups;
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return 0;
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}
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static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
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unsigned pin,
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u8 config)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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unsigned long flags;
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u32 val, mask;
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spin_lock_irqsave(&pctl->lock, flags);
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val = readl(pctl->membase + sunxi_mux_reg(pin));
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mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
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writel((val & ~mask) | config << sunxi_mux_offset(pin),
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pctl->membase + sunxi_mux_reg(pin));
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spin_unlock_irqrestore(&pctl->lock, flags);
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}
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static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
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unsigned function,
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unsigned group)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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struct sunxi_pinctrl_group *g = pctl->groups + group;
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struct sunxi_pinctrl_function *func = pctl->functions + function;
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struct sunxi_desc_function *desc =
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sunxi_pinctrl_desc_find_function_by_name(pctl,
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g->name,
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func->name);
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if (!desc)
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return -EINVAL;
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sunxi_pmx_set(pctldev, g->pin, desc->muxval);
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return 0;
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}
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static int
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sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset,
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bool input)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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struct sunxi_desc_function *desc;
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const char *func;
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if (input)
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func = "gpio_in";
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else
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func = "gpio_out";
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desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
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if (!desc)
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return -EINVAL;
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|
|
sunxi_pmx_set(pctldev, offset, desc->muxval);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pinmux_ops sunxi_pmx_ops = {
|
|
.get_functions_count = sunxi_pmx_get_funcs_cnt,
|
|
.get_function_name = sunxi_pmx_get_func_name,
|
|
.get_function_groups = sunxi_pmx_get_func_groups,
|
|
.enable = sunxi_pmx_enable,
|
|
.gpio_set_direction = sunxi_pmx_gpio_set_direction,
|
|
};
|
|
|
|
static struct pinctrl_desc sunxi_pctrl_desc = {
|
|
.confops = &sunxi_pconf_ops,
|
|
.pctlops = &sunxi_pctrl_ops,
|
|
.pmxops = &sunxi_pmx_ops,
|
|
};
|
|
|
|
static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
return pinctrl_request_gpio(chip->base + offset);
|
|
}
|
|
|
|
static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
pinctrl_free_gpio(chip->base + offset);
|
|
}
|
|
|
|
static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
|
|
unsigned offset)
|
|
{
|
|
return pinctrl_gpio_direction_input(chip->base + offset);
|
|
}
|
|
|
|
static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
|
|
|
|
u32 reg = sunxi_data_reg(offset);
|
|
u8 index = sunxi_data_offset(offset);
|
|
u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
|
|
|
|
return val;
|
|
}
|
|
|
|
static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
|
|
unsigned offset, int value)
|
|
{
|
|
struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
|
|
u32 reg = sunxi_data_reg(offset);
|
|
u8 index = sunxi_data_offset(offset);
|
|
unsigned long flags;
|
|
u32 regval;
|
|
|
|
spin_lock_irqsave(&pctl->lock, flags);
|
|
|
|
regval = readl(pctl->membase + reg);
|
|
|
|
if (value)
|
|
regval |= BIT(index);
|
|
else
|
|
regval &= ~(BIT(index));
|
|
|
|
writel(regval, pctl->membase + reg);
|
|
|
|
spin_unlock_irqrestore(&pctl->lock, flags);
|
|
}
|
|
|
|
static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
|
|
unsigned offset, int value)
|
|
{
|
|
sunxi_pinctrl_gpio_set(chip, offset, value);
|
|
return pinctrl_gpio_direction_output(chip->base + offset);
|
|
}
|
|
|
|
static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
|
|
const struct of_phandle_args *gpiospec,
|
|
u32 *flags)
|
|
{
|
|
int pin, base;
|
|
|
|
base = PINS_PER_BANK * gpiospec->args[0];
|
|
pin = base + gpiospec->args[1];
|
|
|
|
if (pin > (gc->base + gc->ngpio))
|
|
return -EINVAL;
|
|
|
|
if (flags)
|
|
*flags = gpiospec->args[2];
|
|
|
|
return pin;
|
|
}
|
|
|
|
static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
|
|
struct sunxi_desc_function *desc;
|
|
|
|
if (offset >= chip->ngpio)
|
|
return -ENXIO;
|
|
|
|
desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq");
|
|
if (!desc)
|
|
return -EINVAL;
|
|
|
|
pctl->irq_array[desc->irqnum] = offset;
|
|
|
|
dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
|
|
chip->label, offset + chip->base, desc->irqnum);
|
|
|
|
return irq_find_mapping(pctl->domain, desc->irqnum);
|
|
}
|
|
|
|
static struct gpio_chip sunxi_pinctrl_gpio_chip = {
|
|
.owner = THIS_MODULE,
|
|
.request = sunxi_pinctrl_gpio_request,
|
|
.free = sunxi_pinctrl_gpio_free,
|
|
.direction_input = sunxi_pinctrl_gpio_direction_input,
|
|
.direction_output = sunxi_pinctrl_gpio_direction_output,
|
|
.get = sunxi_pinctrl_gpio_get,
|
|
.set = sunxi_pinctrl_gpio_set,
|
|
.of_xlate = sunxi_pinctrl_gpio_of_xlate,
|
|
.to_irq = sunxi_pinctrl_gpio_to_irq,
|
|
.of_gpio_n_cells = 3,
|
|
.can_sleep = false,
|
|
};
|
|
|
|
static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
|
|
unsigned int type)
|
|
{
|
|
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
|
u32 reg = sunxi_irq_cfg_reg(d->hwirq);
|
|
u8 index = sunxi_irq_cfg_offset(d->hwirq);
|
|
unsigned long flags;
|
|
u32 regval;
|
|
u8 mode;
|
|
|
|
switch (type) {
|
|
case IRQ_TYPE_EDGE_RISING:
|
|
mode = IRQ_EDGE_RISING;
|
|
break;
|
|
case IRQ_TYPE_EDGE_FALLING:
|
|
mode = IRQ_EDGE_FALLING;
|
|
break;
|
|
case IRQ_TYPE_EDGE_BOTH:
|
|
mode = IRQ_EDGE_BOTH;
|
|
break;
|
|
case IRQ_TYPE_LEVEL_HIGH:
|
|
mode = IRQ_LEVEL_HIGH;
|
|
break;
|
|
case IRQ_TYPE_LEVEL_LOW:
|
|
mode = IRQ_LEVEL_LOW;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
spin_lock_irqsave(&pctl->lock, flags);
|
|
|
|
regval = readl(pctl->membase + reg);
|
|
regval &= ~IRQ_CFG_IRQ_MASK;
|
|
writel(regval | (mode << index), pctl->membase + reg);
|
|
|
|
spin_unlock_irqrestore(&pctl->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d)
|
|
{
|
|
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
|
u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq);
|
|
u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq);
|
|
u32 status_reg = sunxi_irq_status_reg(d->hwirq);
|
|
u8 status_idx = sunxi_irq_status_offset(d->hwirq);
|
|
unsigned long flags;
|
|
u32 val;
|
|
|
|
spin_lock_irqsave(&pctl->lock, flags);
|
|
|
|
/* Mask the IRQ */
|
|
val = readl(pctl->membase + ctrl_reg);
|
|
writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg);
|
|
|
|
/* Clear the IRQ */
|
|
writel(1 << status_idx, pctl->membase + status_reg);
|
|
|
|
spin_unlock_irqrestore(&pctl->lock, flags);
|
|
}
|
|
|
|
static void sunxi_pinctrl_irq_mask(struct irq_data *d)
|
|
{
|
|
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
|
u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
|
|
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
|
|
unsigned long flags;
|
|
u32 val;
|
|
|
|
spin_lock_irqsave(&pctl->lock, flags);
|
|
|
|
/* Mask the IRQ */
|
|
val = readl(pctl->membase + reg);
|
|
writel(val & ~(1 << idx), pctl->membase + reg);
|
|
|
|
spin_unlock_irqrestore(&pctl->lock, flags);
|
|
}
|
|
|
|
static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
|
|
{
|
|
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
|
struct sunxi_desc_function *func;
|
|
u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
|
|
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
|
|
unsigned long flags;
|
|
u32 val;
|
|
|
|
func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
|
|
pctl->irq_array[d->hwirq],
|
|
"irq");
|
|
|
|
/* Change muxing to INT mode */
|
|
sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
|
|
|
|
spin_lock_irqsave(&pctl->lock, flags);
|
|
|
|
/* Unmask the IRQ */
|
|
val = readl(pctl->membase + reg);
|
|
writel(val | (1 << idx), pctl->membase + reg);
|
|
|
|
spin_unlock_irqrestore(&pctl->lock, flags);
|
|
}
|
|
|
|
static struct irq_chip sunxi_pinctrl_irq_chip = {
|
|
.irq_mask = sunxi_pinctrl_irq_mask,
|
|
.irq_mask_ack = sunxi_pinctrl_irq_mask_ack,
|
|
.irq_unmask = sunxi_pinctrl_irq_unmask,
|
|
.irq_set_type = sunxi_pinctrl_irq_set_type,
|
|
};
|
|
|
|
static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
|
|
{
|
|
struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
|
|
const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG);
|
|
|
|
/* Clear all interrupts */
|
|
writel(reg, pctl->membase + IRQ_STATUS_REG);
|
|
|
|
if (reg) {
|
|
int irqoffset;
|
|
|
|
for_each_set_bit(irqoffset, ®, SUNXI_IRQ_NUMBER) {
|
|
int pin_irq = irq_find_mapping(pctl->domain, irqoffset);
|
|
generic_handle_irq(pin_irq);
|
|
}
|
|
}
|
|
}
|
|
|
|
static struct of_device_id sunxi_pinctrl_match[] = {
|
|
{ .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data },
|
|
{ .compatible = "allwinner,sun5i-a10s-pinctrl", .data = (void *)&sun5i_a10s_pinctrl_data },
|
|
{ .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
|
|
{ .compatible = "allwinner,sun6i-a31-pinctrl", .data = (void *)&sun6i_a31_pinctrl_data },
|
|
{ .compatible = "allwinner,sun7i-a20-pinctrl", .data = (void *)&sun7i_a20_pinctrl_data },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match);
|
|
|
|
static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
|
|
const char *name)
|
|
{
|
|
struct sunxi_pinctrl_function *func = pctl->functions;
|
|
|
|
while (func->name) {
|
|
/* function already there */
|
|
if (strcmp(func->name, name) == 0) {
|
|
func->ngroups++;
|
|
return -EEXIST;
|
|
}
|
|
func++;
|
|
}
|
|
|
|
func->name = name;
|
|
func->ngroups = 1;
|
|
|
|
pctl->nfunctions++;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_pinctrl_build_state(struct platform_device *pdev)
|
|
{
|
|
struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
|
|
int i;
|
|
|
|
pctl->ngroups = pctl->desc->npins;
|
|
|
|
/* Allocate groups */
|
|
pctl->groups = devm_kzalloc(&pdev->dev,
|
|
pctl->ngroups * sizeof(*pctl->groups),
|
|
GFP_KERNEL);
|
|
if (!pctl->groups)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
struct sunxi_pinctrl_group *group = pctl->groups + i;
|
|
|
|
group->name = pin->pin.name;
|
|
group->pin = pin->pin.number;
|
|
}
|
|
|
|
/*
|
|
* We suppose that we won't have any more functions than pins,
|
|
* we'll reallocate that later anyway
|
|
*/
|
|
pctl->functions = devm_kzalloc(&pdev->dev,
|
|
pctl->desc->npins * sizeof(*pctl->functions),
|
|
GFP_KERNEL);
|
|
if (!pctl->functions)
|
|
return -ENOMEM;
|
|
|
|
/* Count functions and their associated groups */
|
|
for (i = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
struct sunxi_desc_function *func = pin->functions;
|
|
|
|
while (func->name) {
|
|
sunxi_pinctrl_add_function(pctl, func->name);
|
|
func++;
|
|
}
|
|
}
|
|
|
|
pctl->functions = krealloc(pctl->functions,
|
|
pctl->nfunctions * sizeof(*pctl->functions),
|
|
GFP_KERNEL);
|
|
|
|
for (i = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
struct sunxi_desc_function *func = pin->functions;
|
|
|
|
while (func->name) {
|
|
struct sunxi_pinctrl_function *func_item;
|
|
const char **func_grp;
|
|
|
|
func_item = sunxi_pinctrl_find_function_by_name(pctl,
|
|
func->name);
|
|
if (!func_item)
|
|
return -EINVAL;
|
|
|
|
if (!func_item->groups) {
|
|
func_item->groups =
|
|
devm_kzalloc(&pdev->dev,
|
|
func_item->ngroups * sizeof(*func_item->groups),
|
|
GFP_KERNEL);
|
|
if (!func_item->groups)
|
|
return -ENOMEM;
|
|
}
|
|
|
|
func_grp = func_item->groups;
|
|
while (*func_grp)
|
|
func_grp++;
|
|
|
|
*func_grp = pin->pin.name;
|
|
func++;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_pinctrl_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *node = pdev->dev.of_node;
|
|
const struct of_device_id *device;
|
|
struct pinctrl_pin_desc *pins;
|
|
struct sunxi_pinctrl *pctl;
|
|
int i, ret, last_pin;
|
|
struct clk *clk;
|
|
|
|
pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
|
|
if (!pctl)
|
|
return -ENOMEM;
|
|
platform_set_drvdata(pdev, pctl);
|
|
|
|
spin_lock_init(&pctl->lock);
|
|
|
|
pctl->membase = of_iomap(node, 0);
|
|
if (!pctl->membase)
|
|
return -ENOMEM;
|
|
|
|
device = of_match_device(sunxi_pinctrl_match, &pdev->dev);
|
|
if (!device)
|
|
return -ENODEV;
|
|
|
|
pctl->desc = (struct sunxi_pinctrl_desc *)device->data;
|
|
|
|
ret = sunxi_pinctrl_build_state(pdev);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
pins = devm_kzalloc(&pdev->dev,
|
|
pctl->desc->npins * sizeof(*pins),
|
|
GFP_KERNEL);
|
|
if (!pins)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < pctl->desc->npins; i++)
|
|
pins[i] = pctl->desc->pins[i].pin;
|
|
|
|
sunxi_pctrl_desc.name = dev_name(&pdev->dev);
|
|
sunxi_pctrl_desc.owner = THIS_MODULE;
|
|
sunxi_pctrl_desc.pins = pins;
|
|
sunxi_pctrl_desc.npins = pctl->desc->npins;
|
|
pctl->dev = &pdev->dev;
|
|
pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc,
|
|
&pdev->dev, pctl);
|
|
if (!pctl->pctl_dev) {
|
|
dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
|
|
if (!pctl->chip) {
|
|
ret = -ENOMEM;
|
|
goto pinctrl_error;
|
|
}
|
|
|
|
last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
|
|
pctl->chip = &sunxi_pinctrl_gpio_chip;
|
|
pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK);
|
|
pctl->chip->label = dev_name(&pdev->dev);
|
|
pctl->chip->dev = &pdev->dev;
|
|
pctl->chip->base = 0;
|
|
|
|
ret = gpiochip_add(pctl->chip);
|
|
if (ret)
|
|
goto pinctrl_error;
|
|
|
|
for (i = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
|
|
ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
|
|
pin->pin.number,
|
|
pin->pin.number, 1);
|
|
if (ret)
|
|
goto gpiochip_error;
|
|
}
|
|
|
|
clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(clk)) {
|
|
ret = PTR_ERR(clk);
|
|
goto gpiochip_error;
|
|
}
|
|
|
|
clk_prepare_enable(clk);
|
|
|
|
pctl->irq = irq_of_parse_and_map(node, 0);
|
|
if (!pctl->irq) {
|
|
ret = -EINVAL;
|
|
goto gpiochip_error;
|
|
}
|
|
|
|
pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
|
|
&irq_domain_simple_ops, NULL);
|
|
if (!pctl->domain) {
|
|
dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
|
|
ret = -ENOMEM;
|
|
goto gpiochip_error;
|
|
}
|
|
|
|
for (i = 0; i < SUNXI_IRQ_NUMBER; i++) {
|
|
int irqno = irq_create_mapping(pctl->domain, i);
|
|
|
|
irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip,
|
|
handle_simple_irq);
|
|
irq_set_chip_data(irqno, pctl);
|
|
};
|
|
|
|
irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler);
|
|
irq_set_handler_data(pctl->irq, pctl);
|
|
|
|
dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
|
|
|
|
return 0;
|
|
|
|
gpiochip_error:
|
|
if (gpiochip_remove(pctl->chip))
|
|
dev_err(&pdev->dev, "failed to remove gpio chip\n");
|
|
pinctrl_error:
|
|
pinctrl_unregister(pctl->pctl_dev);
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver sunxi_pinctrl_driver = {
|
|
.probe = sunxi_pinctrl_probe,
|
|
.driver = {
|
|
.name = "sunxi-pinctrl",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = sunxi_pinctrl_match,
|
|
},
|
|
};
|
|
module_platform_driver(sunxi_pinctrl_driver);
|
|
|
|
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
|
|
MODULE_DESCRIPTION("Allwinner A1X pinctrl driver");
|
|
MODULE_LICENSE("GPL");
|