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![Hanjun Guo](/assets/img/avatar_default.png)
Convert to module_platform_driver() to simplify code. Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
806 lines
19 KiB
C
806 lines
19 KiB
C
/*
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* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 SoC LCD framebuffer driver
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/console.h>
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#include <linux/fb.h>
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#include <linux/dma-mapping.h>
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#include <asm/mach-jz4740/jz4740_fb.h>
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#include <asm/mach-jz4740/gpio.h>
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#define JZ_REG_LCD_CFG 0x00
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#define JZ_REG_LCD_VSYNC 0x04
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#define JZ_REG_LCD_HSYNC 0x08
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#define JZ_REG_LCD_VAT 0x0C
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#define JZ_REG_LCD_DAH 0x10
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#define JZ_REG_LCD_DAV 0x14
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#define JZ_REG_LCD_PS 0x18
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#define JZ_REG_LCD_CLS 0x1C
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#define JZ_REG_LCD_SPL 0x20
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#define JZ_REG_LCD_REV 0x24
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#define JZ_REG_LCD_CTRL 0x30
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#define JZ_REG_LCD_STATE 0x34
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#define JZ_REG_LCD_IID 0x38
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#define JZ_REG_LCD_DA0 0x40
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#define JZ_REG_LCD_SA0 0x44
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#define JZ_REG_LCD_FID0 0x48
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#define JZ_REG_LCD_CMD0 0x4C
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#define JZ_REG_LCD_DA1 0x50
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#define JZ_REG_LCD_SA1 0x54
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#define JZ_REG_LCD_FID1 0x58
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#define JZ_REG_LCD_CMD1 0x5C
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#define JZ_LCD_CFG_SLCD BIT(31)
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#define JZ_LCD_CFG_PS_DISABLE BIT(23)
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#define JZ_LCD_CFG_CLS_DISABLE BIT(22)
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#define JZ_LCD_CFG_SPL_DISABLE BIT(21)
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#define JZ_LCD_CFG_REV_DISABLE BIT(20)
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#define JZ_LCD_CFG_HSYNCM BIT(19)
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#define JZ_LCD_CFG_PCLKM BIT(18)
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#define JZ_LCD_CFG_INV BIT(17)
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#define JZ_LCD_CFG_SYNC_DIR BIT(16)
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#define JZ_LCD_CFG_PS_POLARITY BIT(15)
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#define JZ_LCD_CFG_CLS_POLARITY BIT(14)
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#define JZ_LCD_CFG_SPL_POLARITY BIT(13)
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#define JZ_LCD_CFG_REV_POLARITY BIT(12)
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#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11)
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#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10)
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#define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9)
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#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8)
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#define JZ_LCD_CFG_18_BIT BIT(7)
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#define JZ_LCD_CFG_PDW (BIT(5) | BIT(4))
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#define JZ_LCD_CFG_MODE_MASK 0xf
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#define JZ_LCD_CTRL_BURST_4 (0x0 << 28)
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#define JZ_LCD_CTRL_BURST_8 (0x1 << 28)
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#define JZ_LCD_CTRL_BURST_16 (0x2 << 28)
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#define JZ_LCD_CTRL_RGB555 BIT(27)
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#define JZ_LCD_CTRL_OFUP BIT(26)
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#define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24)
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#define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24)
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#define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24)
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#define JZ_LCD_CTRL_PDD_MASK (0xff << 16)
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#define JZ_LCD_CTRL_EOF_IRQ BIT(13)
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#define JZ_LCD_CTRL_SOF_IRQ BIT(12)
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#define JZ_LCD_CTRL_OFU_IRQ BIT(11)
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#define JZ_LCD_CTRL_IFU0_IRQ BIT(10)
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#define JZ_LCD_CTRL_IFU1_IRQ BIT(9)
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#define JZ_LCD_CTRL_DD_IRQ BIT(8)
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#define JZ_LCD_CTRL_QDD_IRQ BIT(7)
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#define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6)
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#define JZ_LCD_CTRL_LSB_FISRT BIT(5)
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#define JZ_LCD_CTRL_DISABLE BIT(4)
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#define JZ_LCD_CTRL_ENABLE BIT(3)
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#define JZ_LCD_CTRL_BPP_1 0x0
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#define JZ_LCD_CTRL_BPP_2 0x1
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#define JZ_LCD_CTRL_BPP_4 0x2
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#define JZ_LCD_CTRL_BPP_8 0x3
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#define JZ_LCD_CTRL_BPP_15_16 0x4
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#define JZ_LCD_CTRL_BPP_18_24 0x5
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#define JZ_LCD_CMD_SOF_IRQ BIT(31)
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#define JZ_LCD_CMD_EOF_IRQ BIT(30)
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#define JZ_LCD_CMD_ENABLE_PAL BIT(28)
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#define JZ_LCD_SYNC_MASK 0x3ff
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#define JZ_LCD_STATE_DISABLED BIT(0)
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struct jzfb_framedesc {
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uint32_t next;
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uint32_t addr;
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uint32_t id;
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uint32_t cmd;
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} __packed;
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struct jzfb {
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struct fb_info *fb;
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struct platform_device *pdev;
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void __iomem *base;
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struct resource *mem;
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struct jz4740_fb_platform_data *pdata;
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size_t vidmem_size;
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void *vidmem;
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dma_addr_t vidmem_phys;
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struct jzfb_framedesc *framedesc;
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dma_addr_t framedesc_phys;
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struct clk *ldclk;
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struct clk *lpclk;
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unsigned is_enabled:1;
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struct mutex lock;
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uint32_t pseudo_palette[16];
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};
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static const struct fb_fix_screeninfo jzfb_fix = {
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.id = "JZ4740 FB",
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.type = FB_TYPE_PACKED_PIXELS,
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.visual = FB_VISUAL_TRUECOLOR,
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.xpanstep = 0,
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.ypanstep = 0,
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.ywrapstep = 0,
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.accel = FB_ACCEL_NONE,
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};
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static const struct jz_gpio_bulk_request jz_lcd_ctrl_pins[] = {
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JZ_GPIO_BULK_PIN(LCD_PCLK),
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JZ_GPIO_BULK_PIN(LCD_HSYNC),
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JZ_GPIO_BULK_PIN(LCD_VSYNC),
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JZ_GPIO_BULK_PIN(LCD_DE),
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JZ_GPIO_BULK_PIN(LCD_PS),
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JZ_GPIO_BULK_PIN(LCD_REV),
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JZ_GPIO_BULK_PIN(LCD_CLS),
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JZ_GPIO_BULK_PIN(LCD_SPL),
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};
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static const struct jz_gpio_bulk_request jz_lcd_data_pins[] = {
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JZ_GPIO_BULK_PIN(LCD_DATA0),
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JZ_GPIO_BULK_PIN(LCD_DATA1),
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JZ_GPIO_BULK_PIN(LCD_DATA2),
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JZ_GPIO_BULK_PIN(LCD_DATA3),
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JZ_GPIO_BULK_PIN(LCD_DATA4),
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JZ_GPIO_BULK_PIN(LCD_DATA5),
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JZ_GPIO_BULK_PIN(LCD_DATA6),
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JZ_GPIO_BULK_PIN(LCD_DATA7),
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JZ_GPIO_BULK_PIN(LCD_DATA8),
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JZ_GPIO_BULK_PIN(LCD_DATA9),
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JZ_GPIO_BULK_PIN(LCD_DATA10),
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JZ_GPIO_BULK_PIN(LCD_DATA11),
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JZ_GPIO_BULK_PIN(LCD_DATA12),
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JZ_GPIO_BULK_PIN(LCD_DATA13),
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JZ_GPIO_BULK_PIN(LCD_DATA14),
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JZ_GPIO_BULK_PIN(LCD_DATA15),
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JZ_GPIO_BULK_PIN(LCD_DATA16),
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JZ_GPIO_BULK_PIN(LCD_DATA17),
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};
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static unsigned int jzfb_num_ctrl_pins(struct jzfb *jzfb)
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{
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unsigned int num;
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switch (jzfb->pdata->lcd_type) {
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case JZ_LCD_TYPE_GENERIC_16_BIT:
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num = 4;
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break;
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case JZ_LCD_TYPE_GENERIC_18_BIT:
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num = 4;
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break;
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case JZ_LCD_TYPE_8BIT_SERIAL:
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num = 3;
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break;
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case JZ_LCD_TYPE_SPECIAL_TFT_1:
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case JZ_LCD_TYPE_SPECIAL_TFT_2:
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case JZ_LCD_TYPE_SPECIAL_TFT_3:
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num = 8;
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break;
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default:
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num = 0;
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break;
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}
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return num;
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}
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static unsigned int jzfb_num_data_pins(struct jzfb *jzfb)
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{
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unsigned int num;
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switch (jzfb->pdata->lcd_type) {
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case JZ_LCD_TYPE_GENERIC_16_BIT:
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num = 16;
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break;
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case JZ_LCD_TYPE_GENERIC_18_BIT:
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num = 18;
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break;
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case JZ_LCD_TYPE_8BIT_SERIAL:
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num = 8;
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break;
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case JZ_LCD_TYPE_SPECIAL_TFT_1:
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case JZ_LCD_TYPE_SPECIAL_TFT_2:
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case JZ_LCD_TYPE_SPECIAL_TFT_3:
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if (jzfb->pdata->bpp == 18)
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num = 18;
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else
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num = 16;
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break;
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default:
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num = 0;
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break;
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}
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return num;
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}
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/* Based on CNVT_TOHW macro from skeletonfb.c */
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static inline uint32_t jzfb_convert_color_to_hw(unsigned val,
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struct fb_bitfield *bf)
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{
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return (((val << bf->length) + 0x7FFF - val) >> 16) << bf->offset;
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}
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static int jzfb_setcolreg(unsigned regno, unsigned red, unsigned green,
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unsigned blue, unsigned transp, struct fb_info *fb)
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{
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uint32_t color;
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if (regno >= 16)
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return -EINVAL;
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color = jzfb_convert_color_to_hw(red, &fb->var.red);
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color |= jzfb_convert_color_to_hw(green, &fb->var.green);
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color |= jzfb_convert_color_to_hw(blue, &fb->var.blue);
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color |= jzfb_convert_color_to_hw(transp, &fb->var.transp);
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((uint32_t *)(fb->pseudo_palette))[regno] = color;
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return 0;
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}
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static int jzfb_get_controller_bpp(struct jzfb *jzfb)
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{
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switch (jzfb->pdata->bpp) {
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case 18:
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case 24:
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return 32;
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case 15:
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return 16;
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default:
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return jzfb->pdata->bpp;
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}
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}
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static struct fb_videomode *jzfb_get_mode(struct jzfb *jzfb,
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struct fb_var_screeninfo *var)
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{
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size_t i;
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struct fb_videomode *mode = jzfb->pdata->modes;
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for (i = 0; i < jzfb->pdata->num_modes; ++i, ++mode) {
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if (mode->xres == var->xres && mode->yres == var->yres)
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return mode;
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}
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return NULL;
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}
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static int jzfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb)
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{
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struct jzfb *jzfb = fb->par;
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struct fb_videomode *mode;
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if (var->bits_per_pixel != jzfb_get_controller_bpp(jzfb) &&
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var->bits_per_pixel != jzfb->pdata->bpp)
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return -EINVAL;
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mode = jzfb_get_mode(jzfb, var);
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if (mode == NULL)
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return -EINVAL;
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fb_videomode_to_var(var, mode);
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switch (jzfb->pdata->bpp) {
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case 8:
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break;
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case 15:
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var->red.offset = 10;
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var->red.length = 5;
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var->green.offset = 6;
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var->green.length = 5;
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var->blue.offset = 0;
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var->blue.length = 5;
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break;
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case 16:
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var->red.offset = 11;
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var->red.length = 5;
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var->green.offset = 5;
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var->green.length = 6;
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var->blue.offset = 0;
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var->blue.length = 5;
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break;
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case 18:
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var->red.offset = 16;
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var->red.length = 6;
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var->green.offset = 8;
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var->green.length = 6;
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var->blue.offset = 0;
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var->blue.length = 6;
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var->bits_per_pixel = 32;
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break;
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case 32:
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case 24:
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var->transp.offset = 24;
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var->transp.length = 8;
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var->red.offset = 16;
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var->red.length = 8;
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var->green.offset = 8;
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var->green.length = 8;
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var->blue.offset = 0;
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var->blue.length = 8;
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var->bits_per_pixel = 32;
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break;
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default:
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break;
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}
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return 0;
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}
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static int jzfb_set_par(struct fb_info *info)
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{
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struct jzfb *jzfb = info->par;
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struct jz4740_fb_platform_data *pdata = jzfb->pdata;
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struct fb_var_screeninfo *var = &info->var;
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struct fb_videomode *mode;
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uint16_t hds, vds;
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uint16_t hde, vde;
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uint16_t ht, vt;
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uint32_t ctrl;
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uint32_t cfg;
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unsigned long rate;
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mode = jzfb_get_mode(jzfb, var);
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if (mode == NULL)
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return -EINVAL;
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if (mode == info->mode)
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return 0;
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info->mode = mode;
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hds = mode->hsync_len + mode->left_margin;
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hde = hds + mode->xres;
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ht = hde + mode->right_margin;
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vds = mode->vsync_len + mode->upper_margin;
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vde = vds + mode->yres;
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vt = vde + mode->lower_margin;
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ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16;
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switch (pdata->bpp) {
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case 1:
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ctrl |= JZ_LCD_CTRL_BPP_1;
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break;
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case 2:
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ctrl |= JZ_LCD_CTRL_BPP_2;
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break;
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case 4:
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ctrl |= JZ_LCD_CTRL_BPP_4;
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break;
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case 8:
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ctrl |= JZ_LCD_CTRL_BPP_8;
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break;
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case 15:
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ctrl |= JZ_LCD_CTRL_RGB555; /* Falltrough */
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case 16:
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ctrl |= JZ_LCD_CTRL_BPP_15_16;
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break;
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case 18:
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case 24:
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case 32:
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ctrl |= JZ_LCD_CTRL_BPP_18_24;
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break;
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default:
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break;
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}
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cfg = pdata->lcd_type & 0xf;
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if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
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cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
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if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
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cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW;
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if (pdata->pixclk_falling_edge)
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cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
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if (pdata->date_enable_active_low)
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cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW;
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if (pdata->lcd_type == JZ_LCD_TYPE_GENERIC_18_BIT)
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cfg |= JZ_LCD_CFG_18_BIT;
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if (mode->pixclock) {
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rate = PICOS2KHZ(mode->pixclock) * 1000;
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mode->refresh = rate / vt / ht;
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} else {
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if (pdata->lcd_type == JZ_LCD_TYPE_8BIT_SERIAL)
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rate = mode->refresh * (vt + 2 * mode->xres) * ht;
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else
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rate = mode->refresh * vt * ht;
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mode->pixclock = KHZ2PICOS(rate / 1000);
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}
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mutex_lock(&jzfb->lock);
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if (!jzfb->is_enabled)
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clk_enable(jzfb->ldclk);
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else
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ctrl |= JZ_LCD_CTRL_ENABLE;
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switch (pdata->lcd_type) {
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case JZ_LCD_TYPE_SPECIAL_TFT_1:
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case JZ_LCD_TYPE_SPECIAL_TFT_2:
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case JZ_LCD_TYPE_SPECIAL_TFT_3:
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writel(pdata->special_tft_config.spl, jzfb->base + JZ_REG_LCD_SPL);
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writel(pdata->special_tft_config.cls, jzfb->base + JZ_REG_LCD_CLS);
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writel(pdata->special_tft_config.ps, jzfb->base + JZ_REG_LCD_PS);
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writel(pdata->special_tft_config.ps, jzfb->base + JZ_REG_LCD_REV);
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break;
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default:
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cfg |= JZ_LCD_CFG_PS_DISABLE;
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cfg |= JZ_LCD_CFG_CLS_DISABLE;
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cfg |= JZ_LCD_CFG_SPL_DISABLE;
|
|
cfg |= JZ_LCD_CFG_REV_DISABLE;
|
|
break;
|
|
}
|
|
|
|
writel(mode->hsync_len, jzfb->base + JZ_REG_LCD_HSYNC);
|
|
writel(mode->vsync_len, jzfb->base + JZ_REG_LCD_VSYNC);
|
|
|
|
writel((ht << 16) | vt, jzfb->base + JZ_REG_LCD_VAT);
|
|
|
|
writel((hds << 16) | hde, jzfb->base + JZ_REG_LCD_DAH);
|
|
writel((vds << 16) | vde, jzfb->base + JZ_REG_LCD_DAV);
|
|
|
|
writel(cfg, jzfb->base + JZ_REG_LCD_CFG);
|
|
|
|
writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL);
|
|
|
|
if (!jzfb->is_enabled)
|
|
clk_disable_unprepare(jzfb->ldclk);
|
|
|
|
mutex_unlock(&jzfb->lock);
|
|
|
|
clk_set_rate(jzfb->lpclk, rate);
|
|
clk_set_rate(jzfb->ldclk, rate * 3);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void jzfb_enable(struct jzfb *jzfb)
|
|
{
|
|
uint32_t ctrl;
|
|
|
|
clk_prepare_enable(jzfb->ldclk);
|
|
|
|
jz_gpio_bulk_resume(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
|
|
jz_gpio_bulk_resume(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
|
|
|
|
writel(0, jzfb->base + JZ_REG_LCD_STATE);
|
|
|
|
writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0);
|
|
|
|
ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL);
|
|
ctrl |= JZ_LCD_CTRL_ENABLE;
|
|
ctrl &= ~JZ_LCD_CTRL_DISABLE;
|
|
writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL);
|
|
}
|
|
|
|
static void jzfb_disable(struct jzfb *jzfb)
|
|
{
|
|
uint32_t ctrl;
|
|
|
|
ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL);
|
|
ctrl |= JZ_LCD_CTRL_DISABLE;
|
|
writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL);
|
|
do {
|
|
ctrl = readl(jzfb->base + JZ_REG_LCD_STATE);
|
|
} while (!(ctrl & JZ_LCD_STATE_DISABLED));
|
|
|
|
jz_gpio_bulk_suspend(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
|
|
jz_gpio_bulk_suspend(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
|
|
|
|
clk_disable_unprepare(jzfb->ldclk);
|
|
}
|
|
|
|
static int jzfb_blank(int blank_mode, struct fb_info *info)
|
|
{
|
|
struct jzfb *jzfb = info->par;
|
|
|
|
switch (blank_mode) {
|
|
case FB_BLANK_UNBLANK:
|
|
mutex_lock(&jzfb->lock);
|
|
if (jzfb->is_enabled) {
|
|
mutex_unlock(&jzfb->lock);
|
|
return 0;
|
|
}
|
|
|
|
jzfb_enable(jzfb);
|
|
jzfb->is_enabled = 1;
|
|
|
|
mutex_unlock(&jzfb->lock);
|
|
break;
|
|
default:
|
|
mutex_lock(&jzfb->lock);
|
|
if (!jzfb->is_enabled) {
|
|
mutex_unlock(&jzfb->lock);
|
|
return 0;
|
|
}
|
|
|
|
jzfb_disable(jzfb);
|
|
jzfb->is_enabled = 0;
|
|
|
|
mutex_unlock(&jzfb->lock);
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int jzfb_alloc_devmem(struct jzfb *jzfb)
|
|
{
|
|
int max_videosize = 0;
|
|
struct fb_videomode *mode = jzfb->pdata->modes;
|
|
void *page;
|
|
int i;
|
|
|
|
for (i = 0; i < jzfb->pdata->num_modes; ++mode, ++i) {
|
|
if (max_videosize < mode->xres * mode->yres)
|
|
max_videosize = mode->xres * mode->yres;
|
|
}
|
|
|
|
max_videosize *= jzfb_get_controller_bpp(jzfb) >> 3;
|
|
|
|
jzfb->framedesc = dma_alloc_coherent(&jzfb->pdev->dev,
|
|
sizeof(*jzfb->framedesc),
|
|
&jzfb->framedesc_phys, GFP_KERNEL);
|
|
|
|
if (!jzfb->framedesc)
|
|
return -ENOMEM;
|
|
|
|
jzfb->vidmem_size = PAGE_ALIGN(max_videosize);
|
|
jzfb->vidmem = dma_alloc_coherent(&jzfb->pdev->dev,
|
|
jzfb->vidmem_size,
|
|
&jzfb->vidmem_phys, GFP_KERNEL);
|
|
|
|
if (!jzfb->vidmem)
|
|
goto err_free_framedesc;
|
|
|
|
for (page = jzfb->vidmem;
|
|
page < jzfb->vidmem + PAGE_ALIGN(jzfb->vidmem_size);
|
|
page += PAGE_SIZE) {
|
|
SetPageReserved(virt_to_page(page));
|
|
}
|
|
|
|
jzfb->framedesc->next = jzfb->framedesc_phys;
|
|
jzfb->framedesc->addr = jzfb->vidmem_phys;
|
|
jzfb->framedesc->id = 0xdeafbead;
|
|
jzfb->framedesc->cmd = 0;
|
|
jzfb->framedesc->cmd |= max_videosize / 4;
|
|
|
|
return 0;
|
|
|
|
err_free_framedesc:
|
|
dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc),
|
|
jzfb->framedesc, jzfb->framedesc_phys);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static void jzfb_free_devmem(struct jzfb *jzfb)
|
|
{
|
|
dma_free_coherent(&jzfb->pdev->dev, jzfb->vidmem_size,
|
|
jzfb->vidmem, jzfb->vidmem_phys);
|
|
dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc),
|
|
jzfb->framedesc, jzfb->framedesc_phys);
|
|
}
|
|
|
|
static struct fb_ops jzfb_ops = {
|
|
.owner = THIS_MODULE,
|
|
.fb_check_var = jzfb_check_var,
|
|
.fb_set_par = jzfb_set_par,
|
|
.fb_blank = jzfb_blank,
|
|
.fb_fillrect = sys_fillrect,
|
|
.fb_copyarea = sys_copyarea,
|
|
.fb_imageblit = sys_imageblit,
|
|
.fb_setcolreg = jzfb_setcolreg,
|
|
};
|
|
|
|
static int jzfb_probe(struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
struct jzfb *jzfb;
|
|
struct fb_info *fb;
|
|
struct jz4740_fb_platform_data *pdata = pdev->dev.platform_data;
|
|
struct resource *mem;
|
|
|
|
if (!pdata) {
|
|
dev_err(&pdev->dev, "Missing platform data\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
fb = framebuffer_alloc(sizeof(struct jzfb), &pdev->dev);
|
|
if (!fb) {
|
|
dev_err(&pdev->dev, "Failed to allocate framebuffer device\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
fb->fbops = &jzfb_ops;
|
|
fb->flags = FBINFO_DEFAULT;
|
|
|
|
jzfb = fb->par;
|
|
jzfb->pdev = pdev;
|
|
jzfb->pdata = pdata;
|
|
|
|
jzfb->ldclk = devm_clk_get(&pdev->dev, "lcd");
|
|
if (IS_ERR(jzfb->ldclk)) {
|
|
ret = PTR_ERR(jzfb->ldclk);
|
|
dev_err(&pdev->dev, "Failed to get lcd clock: %d\n", ret);
|
|
goto err_framebuffer_release;
|
|
}
|
|
|
|
jzfb->lpclk = devm_clk_get(&pdev->dev, "lcd_pclk");
|
|
if (IS_ERR(jzfb->lpclk)) {
|
|
ret = PTR_ERR(jzfb->lpclk);
|
|
dev_err(&pdev->dev, "Failed to get lcd pixel clock: %d\n", ret);
|
|
goto err_framebuffer_release;
|
|
}
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
jzfb->base = devm_ioremap_resource(&pdev->dev, mem);
|
|
if (IS_ERR(jzfb->base)) {
|
|
ret = PTR_ERR(jzfb->base);
|
|
goto err_framebuffer_release;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, jzfb);
|
|
|
|
mutex_init(&jzfb->lock);
|
|
|
|
fb_videomode_to_modelist(pdata->modes, pdata->num_modes,
|
|
&fb->modelist);
|
|
fb_videomode_to_var(&fb->var, pdata->modes);
|
|
fb->var.bits_per_pixel = pdata->bpp;
|
|
jzfb_check_var(&fb->var, fb);
|
|
|
|
ret = jzfb_alloc_devmem(jzfb);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to allocate video memory\n");
|
|
goto err_framebuffer_release;
|
|
}
|
|
|
|
fb->fix = jzfb_fix;
|
|
fb->fix.line_length = fb->var.bits_per_pixel * fb->var.xres / 8;
|
|
fb->fix.mmio_start = mem->start;
|
|
fb->fix.mmio_len = resource_size(mem);
|
|
fb->fix.smem_start = jzfb->vidmem_phys;
|
|
fb->fix.smem_len = fb->fix.line_length * fb->var.yres;
|
|
fb->screen_base = jzfb->vidmem;
|
|
fb->pseudo_palette = jzfb->pseudo_palette;
|
|
|
|
fb_alloc_cmap(&fb->cmap, 256, 0);
|
|
|
|
clk_prepare_enable(jzfb->ldclk);
|
|
jzfb->is_enabled = 1;
|
|
|
|
writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0);
|
|
|
|
fb->mode = NULL;
|
|
jzfb_set_par(fb);
|
|
|
|
jz_gpio_bulk_request(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
|
|
jz_gpio_bulk_request(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
|
|
|
|
ret = register_framebuffer(fb);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register framebuffer: %d\n", ret);
|
|
goto err_free_devmem;
|
|
}
|
|
|
|
jzfb->fb = fb;
|
|
|
|
return 0;
|
|
|
|
err_free_devmem:
|
|
jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
|
|
jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
|
|
|
|
fb_dealloc_cmap(&fb->cmap);
|
|
jzfb_free_devmem(jzfb);
|
|
err_framebuffer_release:
|
|
framebuffer_release(fb);
|
|
return ret;
|
|
}
|
|
|
|
static int jzfb_remove(struct platform_device *pdev)
|
|
{
|
|
struct jzfb *jzfb = platform_get_drvdata(pdev);
|
|
|
|
jzfb_blank(FB_BLANK_POWERDOWN, jzfb->fb);
|
|
|
|
jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
|
|
jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
|
|
|
|
fb_dealloc_cmap(&jzfb->fb->cmap);
|
|
jzfb_free_devmem(jzfb);
|
|
|
|
framebuffer_release(jzfb->fb);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int jzfb_suspend(struct device *dev)
|
|
{
|
|
struct jzfb *jzfb = dev_get_drvdata(dev);
|
|
|
|
console_lock();
|
|
fb_set_suspend(jzfb->fb, 1);
|
|
console_unlock();
|
|
|
|
mutex_lock(&jzfb->lock);
|
|
if (jzfb->is_enabled)
|
|
jzfb_disable(jzfb);
|
|
mutex_unlock(&jzfb->lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int jzfb_resume(struct device *dev)
|
|
{
|
|
struct jzfb *jzfb = dev_get_drvdata(dev);
|
|
clk_prepare_enable(jzfb->ldclk);
|
|
|
|
mutex_lock(&jzfb->lock);
|
|
if (jzfb->is_enabled)
|
|
jzfb_enable(jzfb);
|
|
mutex_unlock(&jzfb->lock);
|
|
|
|
console_lock();
|
|
fb_set_suspend(jzfb->fb, 0);
|
|
console_unlock();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops jzfb_pm_ops = {
|
|
.suspend = jzfb_suspend,
|
|
.resume = jzfb_resume,
|
|
.poweroff = jzfb_suspend,
|
|
.restore = jzfb_resume,
|
|
};
|
|
|
|
#define JZFB_PM_OPS (&jzfb_pm_ops)
|
|
|
|
#else
|
|
#define JZFB_PM_OPS NULL
|
|
#endif
|
|
|
|
static struct platform_driver jzfb_driver = {
|
|
.probe = jzfb_probe,
|
|
.remove = jzfb_remove,
|
|
.driver = {
|
|
.name = "jz4740-fb",
|
|
.pm = JZFB_PM_OPS,
|
|
},
|
|
};
|
|
module_platform_driver(jzfb_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
|
|
MODULE_DESCRIPTION("JZ4740 SoC LCD framebuffer driver");
|
|
MODULE_ALIAS("platform:jz4740-fb");
|