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a45ff5994c
- Add support for chained PMU counters in guests - Improve SError handling - Handle Neoverse N1 erratum #1349291 - Allow side-channel mitigation status to be migrated - Standardise most AArch64 system register accesses to msr_s/mrs_s - Fix host MPIDR corruption on 32bit -----BEGIN PGP SIGNATURE----- iQJJBAABCgAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAl0kge4VHG1hcmMuenlu Z2llckBhcm0uY29tAAoJECPQ0LrRPXpDYyQP/3XY5tFcLKkp/h9rnGaCXwAxhNzn TyF/IZEFBKFTSoDMXKLLc8KllvoPQ7aUl03heYbuayYpyKR1+LCx7lDwu1MYyEf+ aSSuOKlbG//tLUEGp09pTRCgjs2mhhZYqOj5GF2mZ7xpovFVSNOPzTazbXDNQ7tw zUAs43YNg+bUMwj+SLWpBlizjrLr7T34utIr6daKJE/GSfmIrcYXhGbZqUh0zbO0 z5LNasebws8/pHyeGI7+/yoMIKaQ8foMgywTpsRpBsx6YI+AbOLjEmCk2IBOPcEK pm9KkSIBZEO2CSxZKl3NQiEow/Qd/lnz2xLMCSfh4XrYoI2Th4gNcsbJpiBDWP5a 0eZ5jSiexxKngIbM+to7jR3m0yc9RgcuzceJg3Uly7Ya0vb5RqKwOX4Ge4XP4VDT DzIVFdQjxDKdVIf3EvGp1cj4P7dRUU3xbZcbzyuRPEmT3vgjEnbxawmPLs3QMAl1 31Wd2wIsPB86kSxzSMel27Vs5VgMhgyHE26zN91R745CvhDXaDKydIWjGjdVMHsB GuX/h2kL+ohx+N/OpZPgwsVUAGLSOQFP3pE/EcGtqc2kkfqa+bx12DKcZ3zdmJvy +cu5ixU8q5thPH/pZob/C3hKUY/eLy02emS34RK0Jh2sZHbQgAOtMsiqUxNHEjUm 6TkpdWa5SRd7CtGV =yfCs -----END PGP SIGNATURE----- Merge tag 'kvm-arm-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/arm updates for 5.3 - Add support for chained PMU counters in guests - Improve SError handling - Handle Neoverse N1 erratum #1349291 - Allow side-channel mitigation status to be migrated - Standardise most AArch64 system register accesses to msr_s/mrs_s - Fix host MPIDR corruption on 32bit
117 lines
2.9 KiB
C
117 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* irq.h: in kernel interrupt controller related definitions
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* Copyright (c) 2007, Intel Corporation.
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*
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* Authors:
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* Yaozu (Eddie) Dong <Eddie.dong@intel.com>
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*/
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#ifndef __IRQ_H
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#define __IRQ_H
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#include <linux/mm_types.h>
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#include <linux/hrtimer.h>
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#include <linux/kvm_host.h>
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#include <linux/spinlock.h>
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#include <kvm/iodev.h>
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#include "ioapic.h"
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#include "lapic.h"
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#define PIC_NUM_PINS 16
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#define SELECT_PIC(irq) \
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((irq) < 8 ? KVM_IRQCHIP_PIC_MASTER : KVM_IRQCHIP_PIC_SLAVE)
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struct kvm;
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struct kvm_vcpu;
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struct kvm_kpic_state {
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u8 last_irr; /* edge detection */
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u8 irr; /* interrupt request register */
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u8 imr; /* interrupt mask register */
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u8 isr; /* interrupt service register */
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u8 priority_add; /* highest irq priority */
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u8 irq_base;
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u8 read_reg_select;
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u8 poll;
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u8 special_mask;
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u8 init_state;
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u8 auto_eoi;
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u8 rotate_on_auto_eoi;
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u8 special_fully_nested_mode;
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u8 init4; /* true if 4 byte init */
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u8 elcr; /* PIIX edge/trigger selection */
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u8 elcr_mask;
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u8 isr_ack; /* interrupt ack detection */
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struct kvm_pic *pics_state;
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};
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struct kvm_pic {
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spinlock_t lock;
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bool wakeup_needed;
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unsigned pending_acks;
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struct kvm *kvm;
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struct kvm_kpic_state pics[2]; /* 0 is master pic, 1 is slave pic */
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int output; /* intr from master PIC */
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struct kvm_io_device dev_master;
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struct kvm_io_device dev_slave;
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struct kvm_io_device dev_eclr;
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void (*ack_notifier)(void *opaque, int irq);
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unsigned long irq_states[PIC_NUM_PINS];
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};
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int kvm_pic_init(struct kvm *kvm);
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void kvm_pic_destroy(struct kvm *kvm);
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int kvm_pic_read_irq(struct kvm *kvm);
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void kvm_pic_update_irq(struct kvm_pic *s);
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static inline int pic_in_kernel(struct kvm *kvm)
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{
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int mode = kvm->arch.irqchip_mode;
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/* Matches smp_wmb() when setting irqchip_mode */
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smp_rmb();
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return mode == KVM_IRQCHIP_KERNEL;
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}
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static inline int irqchip_split(struct kvm *kvm)
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{
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int mode = kvm->arch.irqchip_mode;
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/* Matches smp_wmb() when setting irqchip_mode */
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smp_rmb();
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return mode == KVM_IRQCHIP_SPLIT;
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}
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static inline int irqchip_kernel(struct kvm *kvm)
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{
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int mode = kvm->arch.irqchip_mode;
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/* Matches smp_wmb() when setting irqchip_mode */
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smp_rmb();
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return mode == KVM_IRQCHIP_KERNEL;
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}
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static inline int irqchip_in_kernel(struct kvm *kvm)
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{
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int mode = kvm->arch.irqchip_mode;
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/* Matches smp_wmb() when setting irqchip_mode */
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smp_rmb();
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return mode != KVM_IRQCHIP_NONE;
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}
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void kvm_inject_pending_timer_irqs(struct kvm_vcpu *vcpu);
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void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu);
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void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu);
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void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu);
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void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu);
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void __kvm_migrate_timers(struct kvm_vcpu *vcpu);
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int apic_has_pending_timer(struct kvm_vcpu *vcpu);
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int kvm_setup_default_irq_routing(struct kvm *kvm);
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int kvm_setup_empty_irq_routing(struct kvm *kvm);
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#endif
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