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![Marc Zyngier](/assets/img/avatar_default.png)
The GICv2m driver is so far limited to a single MSI frame, but nothing prevents an implementation from having several of them. This patch expands the driver to enumerate all frames, keeping the first one as the canonical identifier for the MSI domains. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Tested-by: Duc Dang <dhdang@apm.com> Cc: <linux-arm-kernel@lists.infradead.org> Cc: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1444822037-16983-3-git-send-email-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
402 lines
10 KiB
C
402 lines
10 KiB
C
/*
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* ARM GIC v2m MSI(-X) support
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* Support for Message Signaled Interrupts for systems that
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* implement ARM Generic Interrupt Controller: GICv2m.
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*
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* Copyright (C) 2014 Advanced Micro Devices, Inc.
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* Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
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* Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
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* Brandon Anderson <brandon.anderson@amd.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) "GICv2m: " fmt
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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/*
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* MSI_TYPER:
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* [31:26] Reserved
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* [25:16] lowest SPI assigned to MSI
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* [15:10] Reserved
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* [9:0] Numer of SPIs assigned to MSI
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*/
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#define V2M_MSI_TYPER 0x008
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#define V2M_MSI_TYPER_BASE_SHIFT 16
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#define V2M_MSI_TYPER_BASE_MASK 0x3FF
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#define V2M_MSI_TYPER_NUM_MASK 0x3FF
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#define V2M_MSI_SETSPI_NS 0x040
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#define V2M_MIN_SPI 32
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#define V2M_MAX_SPI 1019
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#define V2M_MSI_IIDR 0xFCC
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#define V2M_MSI_TYPER_BASE_SPI(x) \
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(((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
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#define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK)
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/* APM X-Gene with GICv2m MSI_IIDR register value */
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#define XGENE_GICV2M_MSI_IIDR 0x06000170
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/* List of flags for specific v2m implementation */
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#define GICV2M_NEEDS_SPI_OFFSET 0x00000001
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static LIST_HEAD(v2m_nodes);
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static DEFINE_SPINLOCK(v2m_lock);
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struct v2m_data {
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struct list_head entry;
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struct device_node *node;
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struct resource res; /* GICv2m resource */
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void __iomem *base; /* GICv2m virt address */
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u32 spi_start; /* The SPI number that MSIs start */
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u32 nr_spis; /* The number of SPIs for MSIs */
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unsigned long *bm; /* MSI vector bitmap */
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u32 flags; /* v2m flags for specific implementation */
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};
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static void gicv2m_mask_msi_irq(struct irq_data *d)
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{
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pci_msi_mask_irq(d);
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irq_chip_mask_parent(d);
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}
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static void gicv2m_unmask_msi_irq(struct irq_data *d)
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{
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pci_msi_unmask_irq(d);
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irq_chip_unmask_parent(d);
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}
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static struct irq_chip gicv2m_msi_irq_chip = {
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.name = "MSI",
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.irq_mask = gicv2m_mask_msi_irq,
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.irq_unmask = gicv2m_unmask_msi_irq,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_write_msi_msg = pci_msi_domain_write_msg,
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};
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static struct msi_domain_info gicv2m_msi_domain_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_PCI_MSIX),
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.chip = &gicv2m_msi_irq_chip,
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};
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static int gicv2m_set_affinity(struct irq_data *irq_data,
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const struct cpumask *mask, bool force)
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{
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int ret;
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ret = irq_chip_set_affinity_parent(irq_data, mask, force);
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if (ret == IRQ_SET_MASK_OK)
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ret = IRQ_SET_MASK_OK_DONE;
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return ret;
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}
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static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
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phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;
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msg->address_hi = upper_32_bits(addr);
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msg->address_lo = lower_32_bits(addr);
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msg->data = data->hwirq;
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if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
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msg->data -= v2m->spi_start;
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}
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static struct irq_chip gicv2m_irq_chip = {
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.name = "GICv2m",
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_affinity = gicv2m_set_affinity,
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.irq_compose_msi_msg = gicv2m_compose_msi_msg,
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};
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static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
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unsigned int virq,
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irq_hw_number_t hwirq)
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{
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struct irq_fwspec fwspec;
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struct irq_data *d;
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int err;
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if (is_of_node(domain->parent->fwnode)) {
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fwspec.fwnode = domain->parent->fwnode;
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fwspec.param_count = 3;
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fwspec.param[0] = 0;
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fwspec.param[1] = hwirq - 32;
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fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
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} else {
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return -EINVAL;
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}
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err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
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if (err)
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return err;
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/* Configure the interrupt line to be edge */
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d = irq_domain_get_irq_data(domain->parent, virq);
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d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
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return 0;
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}
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static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq)
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{
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int pos;
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pos = hwirq - v2m->spi_start;
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if (pos < 0 || pos >= v2m->nr_spis) {
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pr_err("Failed to teardown msi. Invalid hwirq %d\n", hwirq);
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return;
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}
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spin_lock(&v2m_lock);
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__clear_bit(pos, v2m->bm);
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spin_unlock(&v2m_lock);
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}
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static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *args)
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{
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struct v2m_data *v2m = NULL, *tmp;
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int hwirq, offset, err = 0;
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spin_lock(&v2m_lock);
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list_for_each_entry(tmp, &v2m_nodes, entry) {
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offset = find_first_zero_bit(tmp->bm, tmp->nr_spis);
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if (offset < tmp->nr_spis) {
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__set_bit(offset, tmp->bm);
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v2m = tmp;
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break;
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}
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}
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spin_unlock(&v2m_lock);
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if (!v2m)
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return -ENOSPC;
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hwirq = v2m->spi_start + offset;
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err = gicv2m_irq_gic_domain_alloc(domain, virq, hwirq);
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if (err) {
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gicv2m_unalloc_msi(v2m, hwirq);
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return err;
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}
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irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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&gicv2m_irq_chip, v2m);
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return 0;
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}
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static void gicv2m_irq_domain_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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struct v2m_data *v2m = irq_data_get_irq_chip_data(d);
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BUG_ON(nr_irqs != 1);
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gicv2m_unalloc_msi(v2m, d->hwirq);
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irq_domain_free_irqs_parent(domain, virq, nr_irqs);
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}
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static const struct irq_domain_ops gicv2m_domain_ops = {
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.alloc = gicv2m_irq_domain_alloc,
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.free = gicv2m_irq_domain_free,
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};
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static bool is_msi_spi_valid(u32 base, u32 num)
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{
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if (base < V2M_MIN_SPI) {
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pr_err("Invalid MSI base SPI (base:%u)\n", base);
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return false;
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}
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if ((num == 0) || (base + num > V2M_MAX_SPI)) {
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pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
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num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
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return false;
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}
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return true;
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}
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static struct irq_chip gicv2m_pmsi_irq_chip = {
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.name = "pMSI",
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};
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static struct msi_domain_ops gicv2m_pmsi_ops = {
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};
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static struct msi_domain_info gicv2m_pmsi_domain_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
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.ops = &gicv2m_pmsi_ops,
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.chip = &gicv2m_pmsi_irq_chip,
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};
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static void gicv2m_teardown(void)
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{
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struct v2m_data *v2m, *tmp;
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list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) {
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list_del(&v2m->entry);
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kfree(v2m->bm);
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iounmap(v2m->base);
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of_node_put(v2m->node);
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kfree(v2m);
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}
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}
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static int gicv2m_allocate_domains(struct irq_domain *parent)
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{
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struct irq_domain *inner_domain, *pci_domain, *plat_domain;
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struct v2m_data *v2m;
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v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
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if (!v2m)
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return 0;
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inner_domain = irq_domain_create_tree(of_node_to_fwnode(v2m->node),
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&gicv2m_domain_ops, v2m);
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if (!inner_domain) {
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pr_err("Failed to create GICv2m domain\n");
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return -ENOMEM;
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}
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inner_domain->bus_token = DOMAIN_BUS_NEXUS;
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inner_domain->parent = parent;
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pci_domain = pci_msi_create_irq_domain(of_node_to_fwnode(v2m->node),
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&gicv2m_msi_domain_info,
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inner_domain);
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plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(v2m->node),
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&gicv2m_pmsi_domain_info,
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inner_domain);
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if (!pci_domain || !plat_domain) {
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pr_err("Failed to create MSI domains\n");
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if (plat_domain)
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irq_domain_remove(plat_domain);
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if (pci_domain)
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irq_domain_remove(pci_domain);
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irq_domain_remove(inner_domain);
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return -ENOMEM;
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}
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return 0;
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}
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static int __init gicv2m_init_one(struct device_node *node,
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struct irq_domain *parent)
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{
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int ret;
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struct v2m_data *v2m;
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v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
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if (!v2m) {
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pr_err("Failed to allocate struct v2m_data.\n");
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return -ENOMEM;
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}
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INIT_LIST_HEAD(&v2m->entry);
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v2m->node = node;
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ret = of_address_to_resource(node, 0, &v2m->res);
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if (ret) {
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pr_err("Failed to allocate v2m resource.\n");
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goto err_free_v2m;
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}
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v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
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if (!v2m->base) {
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pr_err("Failed to map GICv2m resource\n");
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ret = -ENOMEM;
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goto err_free_v2m;
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}
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if (!of_property_read_u32(node, "arm,msi-base-spi", &v2m->spi_start) &&
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!of_property_read_u32(node, "arm,msi-num-spis", &v2m->nr_spis)) {
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pr_info("Overriding V2M MSI_TYPER (base:%u, num:%u)\n",
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v2m->spi_start, v2m->nr_spis);
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} else {
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u32 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
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v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
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v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
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}
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if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
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ret = -EINVAL;
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goto err_iounmap;
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}
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/*
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* APM X-Gene GICv2m implementation has an erratum where
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* the MSI data needs to be the offset from the spi_start
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* in order to trigger the correct MSI interrupt. This is
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* different from the standard GICv2m implementation where
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* the MSI data is the absolute value within the range from
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* spi_start to (spi_start + num_spis).
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*/
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if (readl_relaxed(v2m->base + V2M_MSI_IIDR) == XGENE_GICV2M_MSI_IIDR)
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v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
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v2m->bm = kzalloc(sizeof(long) * BITS_TO_LONGS(v2m->nr_spis),
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GFP_KERNEL);
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if (!v2m->bm) {
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ret = -ENOMEM;
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goto err_iounmap;
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}
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list_add_tail(&v2m->entry, &v2m_nodes);
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pr_info("Node %s: range[%#lx:%#lx], SPI[%d:%d]\n", node->name,
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(unsigned long)v2m->res.start, (unsigned long)v2m->res.end,
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v2m->spi_start, (v2m->spi_start + v2m->nr_spis));
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return 0;
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err_iounmap:
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iounmap(v2m->base);
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err_free_v2m:
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kfree(v2m);
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return ret;
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}
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static struct of_device_id gicv2m_device_id[] = {
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{ .compatible = "arm,gic-v2m-frame", },
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{},
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};
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int __init gicv2m_of_init(struct device_node *node, struct irq_domain *parent)
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{
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int ret = 0;
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struct device_node *child;
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for (child = of_find_matching_node(node, gicv2m_device_id); child;
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child = of_find_matching_node(child, gicv2m_device_id)) {
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if (!of_find_property(child, "msi-controller", NULL))
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continue;
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ret = gicv2m_init_one(child, parent);
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if (ret) {
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of_node_put(node);
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break;
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}
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}
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if (!ret)
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ret = gicv2m_allocate_domains(parent);
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if (ret)
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gicv2m_teardown();
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return ret;
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}
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