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![Axel Lin](/assets/img/avatar_default.png)
Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
237 lines
5.7 KiB
C
237 lines
5.7 KiB
C
/*
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* linux/drivers/gpio/gpio-mb86s7x.c
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*
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* Copyright (C) 2015 Fujitsu Semiconductor Limited
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* Copyright (C) 2015 Linaro Ltd.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/of_device.h>
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#include <linux/gpio/driver.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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/*
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* Only first 8bits of a register correspond to each pin,
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* so there are 4 registers for 32 pins.
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*/
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#define PDR(x) (0x0 + x / 8 * 4)
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#define DDR(x) (0x10 + x / 8 * 4)
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#define PFR(x) (0x20 + x / 8 * 4)
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#define OFFSET(x) BIT((x) % 8)
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struct mb86s70_gpio_chip {
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struct gpio_chip gc;
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void __iomem *base;
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struct clk *clk;
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spinlock_t lock;
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};
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static inline struct mb86s70_gpio_chip *chip_to_mb86s70(struct gpio_chip *gc)
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{
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return container_of(gc, struct mb86s70_gpio_chip, gc);
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}
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static int mb86s70_gpio_request(struct gpio_chip *gc, unsigned gpio)
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{
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struct mb86s70_gpio_chip *gchip = chip_to_mb86s70(gc);
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&gchip->lock, flags);
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val = readl(gchip->base + PFR(gpio));
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if (!(val & OFFSET(gpio))) {
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spin_unlock_irqrestore(&gchip->lock, flags);
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return -EINVAL;
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}
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val &= ~OFFSET(gpio);
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writel(val, gchip->base + PFR(gpio));
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spin_unlock_irqrestore(&gchip->lock, flags);
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return 0;
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}
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static void mb86s70_gpio_free(struct gpio_chip *gc, unsigned gpio)
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{
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struct mb86s70_gpio_chip *gchip = chip_to_mb86s70(gc);
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&gchip->lock, flags);
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val = readl(gchip->base + PFR(gpio));
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val |= OFFSET(gpio);
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writel(val, gchip->base + PFR(gpio));
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spin_unlock_irqrestore(&gchip->lock, flags);
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}
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static int mb86s70_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
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{
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struct mb86s70_gpio_chip *gchip = chip_to_mb86s70(gc);
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unsigned long flags;
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unsigned char val;
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spin_lock_irqsave(&gchip->lock, flags);
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val = readl(gchip->base + DDR(gpio));
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val &= ~OFFSET(gpio);
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writel(val, gchip->base + DDR(gpio));
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spin_unlock_irqrestore(&gchip->lock, flags);
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return 0;
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}
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static int mb86s70_gpio_direction_output(struct gpio_chip *gc,
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unsigned gpio, int value)
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{
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struct mb86s70_gpio_chip *gchip = chip_to_mb86s70(gc);
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unsigned long flags;
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unsigned char val;
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spin_lock_irqsave(&gchip->lock, flags);
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val = readl(gchip->base + PDR(gpio));
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if (value)
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val |= OFFSET(gpio);
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else
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val &= ~OFFSET(gpio);
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writel(val, gchip->base + PDR(gpio));
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val = readl(gchip->base + DDR(gpio));
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val |= OFFSET(gpio);
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writel(val, gchip->base + DDR(gpio));
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spin_unlock_irqrestore(&gchip->lock, flags);
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return 0;
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}
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static int mb86s70_gpio_get(struct gpio_chip *gc, unsigned gpio)
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{
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struct mb86s70_gpio_chip *gchip = chip_to_mb86s70(gc);
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return !!(readl(gchip->base + PDR(gpio)) & OFFSET(gpio));
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}
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static void mb86s70_gpio_set(struct gpio_chip *gc, unsigned gpio, int value)
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{
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struct mb86s70_gpio_chip *gchip = chip_to_mb86s70(gc);
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unsigned long flags;
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unsigned char val;
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spin_lock_irqsave(&gchip->lock, flags);
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val = readl(gchip->base + PDR(gpio));
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if (value)
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val |= OFFSET(gpio);
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else
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val &= ~OFFSET(gpio);
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writel(val, gchip->base + PDR(gpio));
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spin_unlock_irqrestore(&gchip->lock, flags);
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}
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static int mb86s70_gpio_probe(struct platform_device *pdev)
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{
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struct mb86s70_gpio_chip *gchip;
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struct resource *res;
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int ret;
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gchip = devm_kzalloc(&pdev->dev, sizeof(*gchip), GFP_KERNEL);
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if (gchip == NULL)
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return -ENOMEM;
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platform_set_drvdata(pdev, gchip);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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gchip->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(gchip->base))
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return PTR_ERR(gchip->base);
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gchip->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(gchip->clk))
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return PTR_ERR(gchip->clk);
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clk_prepare_enable(gchip->clk);
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spin_lock_init(&gchip->lock);
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gchip->gc.direction_output = mb86s70_gpio_direction_output;
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gchip->gc.direction_input = mb86s70_gpio_direction_input;
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gchip->gc.request = mb86s70_gpio_request;
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gchip->gc.free = mb86s70_gpio_free;
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gchip->gc.get = mb86s70_gpio_get;
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gchip->gc.set = mb86s70_gpio_set;
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gchip->gc.label = dev_name(&pdev->dev);
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gchip->gc.ngpio = 32;
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gchip->gc.owner = THIS_MODULE;
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gchip->gc.dev = &pdev->dev;
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gchip->gc.base = -1;
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platform_set_drvdata(pdev, gchip);
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ret = gpiochip_add(&gchip->gc);
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if (ret) {
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dev_err(&pdev->dev, "couldn't register gpio driver\n");
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clk_disable_unprepare(gchip->clk);
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}
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return ret;
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}
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static int mb86s70_gpio_remove(struct platform_device *pdev)
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{
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struct mb86s70_gpio_chip *gchip = platform_get_drvdata(pdev);
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gpiochip_remove(&gchip->gc);
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clk_disable_unprepare(gchip->clk);
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return 0;
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}
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static const struct of_device_id mb86s70_gpio_dt_ids[] = {
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{ .compatible = "fujitsu,mb86s70-gpio" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, mb86s70_gpio_dt_ids);
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static struct platform_driver mb86s70_gpio_driver = {
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.driver = {
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.name = "mb86s70-gpio",
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.of_match_table = mb86s70_gpio_dt_ids,
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},
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.probe = mb86s70_gpio_probe,
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.remove = mb86s70_gpio_remove,
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};
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static int __init mb86s70_gpio_init(void)
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{
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return platform_driver_register(&mb86s70_gpio_driver);
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}
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module_init(mb86s70_gpio_init);
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MODULE_DESCRIPTION("MB86S7x GPIO Driver");
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MODULE_ALIAS("platform:mb86s70-gpio");
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MODULE_LICENSE("GPL");
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