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![Chang Rebecca Swee Fun](/assets/img/avatar_default.png)
Consolidating similar algorithms into common functions to make GPIO SCH simpler and manageable. Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
244 lines
5.8 KiB
C
244 lines
5.8 KiB
C
/*
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* GPIO interface for Intel Poulsbo SCH
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*
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* Copyright (c) 2010 CompuLab Ltd
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* Author: Denis Turischev <denis@compulab.co.il>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/acpi.h>
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#include <linux/platform_device.h>
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#include <linux/pci_ids.h>
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#include <linux/gpio.h>
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#define GEN 0x00
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#define GIO 0x04
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#define GLV 0x08
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struct sch_gpio {
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struct gpio_chip chip;
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spinlock_t lock;
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unsigned short iobase;
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unsigned short core_base;
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unsigned short resume_base;
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};
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#define to_sch_gpio(gc) container_of(gc, struct sch_gpio, chip)
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static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio,
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unsigned reg)
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{
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unsigned base = 0;
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if (gpio >= sch->resume_base) {
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gpio -= sch->resume_base;
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base += 0x20;
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}
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return base + reg + gpio / 8;
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}
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static unsigned sch_gpio_bit(struct sch_gpio *sch, unsigned gpio)
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{
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if (gpio >= sch->resume_base)
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gpio -= sch->resume_base;
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return gpio % 8;
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}
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static int sch_gpio_reg_get(struct gpio_chip *gc, unsigned gpio, unsigned reg)
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{
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struct sch_gpio *sch = to_sch_gpio(gc);
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unsigned short offset, bit;
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u8 reg_val;
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offset = sch_gpio_offset(sch, gpio, reg);
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bit = sch_gpio_bit(sch, gpio);
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reg_val = !!(inb(sch->iobase + offset) & BIT(bit));
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return reg_val;
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}
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static void sch_gpio_reg_set(struct gpio_chip *gc, unsigned gpio, unsigned reg,
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int val)
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{
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struct sch_gpio *sch = to_sch_gpio(gc);
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unsigned short offset, bit;
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u8 reg_val;
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offset = sch_gpio_offset(sch, gpio, reg);
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bit = sch_gpio_bit(sch, gpio);
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reg_val = inb(sch->iobase + offset);
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if (val)
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outb(reg_val | BIT(bit), sch->iobase + offset);
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else
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outb((reg_val & ~BIT(bit)), sch->iobase + offset);
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}
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static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num)
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{
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struct sch_gpio *sch = to_sch_gpio(gc);
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spin_lock(&sch->lock);
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sch_gpio_reg_set(gc, gpio_num, GIO, 1);
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spin_unlock(&sch->lock);
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return 0;
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}
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static int sch_gpio_get(struct gpio_chip *gc, unsigned gpio_num)
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{
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return sch_gpio_reg_get(gc, gpio_num, GLV);
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}
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static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val)
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{
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struct sch_gpio *sch = to_sch_gpio(gc);
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spin_lock(&sch->lock);
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sch_gpio_reg_set(gc, gpio_num, GLV, val);
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spin_unlock(&sch->lock);
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}
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static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned gpio_num,
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int val)
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{
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struct sch_gpio *sch = to_sch_gpio(gc);
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spin_lock(&sch->lock);
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sch_gpio_reg_set(gc, gpio_num, GIO, 0);
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spin_unlock(&sch->lock);
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/*
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* according to the datasheet, writing to the level register has no
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* effect when GPIO is programmed as input.
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* Actually the the level register is read-only when configured as input.
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* Thus presetting the output level before switching to output is _NOT_ possible.
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* Hence we set the level after configuring the GPIO as output.
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* But we cannot prevent a short low pulse if direction is set to high
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* and an external pull-up is connected.
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*/
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sch_gpio_set(gc, gpio_num, val);
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return 0;
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}
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static struct gpio_chip sch_gpio_chip = {
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.label = "sch_gpio",
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.owner = THIS_MODULE,
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.direction_input = sch_gpio_direction_in,
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.get = sch_gpio_get,
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.direction_output = sch_gpio_direction_out,
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.set = sch_gpio_set,
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};
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static int sch_gpio_probe(struct platform_device *pdev)
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{
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struct sch_gpio *sch;
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struct resource *res;
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sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
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if (!sch)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_IO, 0);
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if (!res)
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return -EBUSY;
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if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
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pdev->name))
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return -EBUSY;
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spin_lock_init(&sch->lock);
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sch->iobase = res->start;
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sch->chip = sch_gpio_chip;
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sch->chip.label = dev_name(&pdev->dev);
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sch->chip.dev = &pdev->dev;
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switch (pdev->id) {
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case PCI_DEVICE_ID_INTEL_SCH_LPC:
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sch->core_base = 0;
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sch->resume_base = 10;
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sch->chip.ngpio = 14;
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/*
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* GPIO[6:0] enabled by default
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* GPIO7 is configured by the CMC as SLPIOVR
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* Enable GPIO[9:8] core powered gpios explicitly
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*/
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sch_gpio_reg_set(&sch->chip, 8, GEN, 1);
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sch_gpio_reg_set(&sch->chip, 9, GEN, 1);
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/*
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* SUS_GPIO[2:0] enabled by default
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* Enable SUS_GPIO3 resume powered gpio explicitly
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*/
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sch_gpio_reg_set(&sch->chip, 13, GEN, 1);
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break;
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case PCI_DEVICE_ID_INTEL_ITC_LPC:
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sch->core_base = 0;
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sch->resume_base = 5;
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sch->chip.ngpio = 14;
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break;
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case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
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sch->core_base = 0;
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sch->resume_base = 21;
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sch->chip.ngpio = 30;
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break;
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case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
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sch->core_base = 0;
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sch->resume_base = 2;
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sch->chip.ngpio = 8;
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break;
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default:
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return -ENODEV;
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}
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platform_set_drvdata(pdev, sch);
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return gpiochip_add(&sch->chip);
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}
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static int sch_gpio_remove(struct platform_device *pdev)
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{
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struct sch_gpio *sch = platform_get_drvdata(pdev);
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gpiochip_remove(&sch->chip);
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return 0;
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}
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static struct platform_driver sch_gpio_driver = {
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.driver = {
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.name = "sch_gpio",
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},
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.probe = sch_gpio_probe,
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.remove = sch_gpio_remove,
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};
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module_platform_driver(sch_gpio_driver);
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MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
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MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:sch_gpio");
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