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![Mathieu Poirier](/assets/img/avatar_default.png)
Keeping drivers related to HW tracing on ARM, i.e coresight, under "drivers/coresight" doesn't make sense when other architectures start rolling out technologies of the same nature. As such creating a new "drivers/hwtracing" directory where all drivers of the same kind can reside, reducing namespace pollution under "drivers/". Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
822 lines
20 KiB
C
822 lines
20 KiB
C
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/fs.h>
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#include <linux/miscdevice.h>
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#include <linux/uaccess.h>
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#include <linux/slab.h>
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#include <linux/dma-mapping.h>
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#include <linux/spinlock.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/coresight.h>
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#include <linux/amba/bus.h>
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#include "coresight-priv.h"
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#define TMC_RSZ 0x004
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#define TMC_STS 0x00c
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#define TMC_RRD 0x010
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#define TMC_RRP 0x014
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#define TMC_RWP 0x018
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#define TMC_TRG 0x01c
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#define TMC_CTL 0x020
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#define TMC_RWD 0x024
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#define TMC_MODE 0x028
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#define TMC_LBUFLEVEL 0x02c
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#define TMC_CBUFLEVEL 0x030
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#define TMC_BUFWM 0x034
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#define TMC_RRPHI 0x038
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#define TMC_RWPHI 0x03c
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#define TMC_AXICTL 0x110
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#define TMC_DBALO 0x118
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#define TMC_DBAHI 0x11c
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#define TMC_FFSR 0x300
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#define TMC_FFCR 0x304
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#define TMC_PSCR 0x308
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#define TMC_ITMISCOP0 0xee0
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#define TMC_ITTRFLIN 0xee8
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#define TMC_ITATBDATA0 0xeec
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#define TMC_ITATBCTR2 0xef0
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#define TMC_ITATBCTR1 0xef4
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#define TMC_ITATBCTR0 0xef8
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/* register description */
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/* TMC_CTL - 0x020 */
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#define TMC_CTL_CAPT_EN BIT(0)
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/* TMC_STS - 0x00C */
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#define TMC_STS_TRIGGERED BIT(1)
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/* TMC_AXICTL - 0x110 */
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#define TMC_AXICTL_PROT_CTL_B0 BIT(0)
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#define TMC_AXICTL_PROT_CTL_B1 BIT(1)
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#define TMC_AXICTL_SCT_GAT_MODE BIT(7)
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#define TMC_AXICTL_WR_BURST_LEN 0xF00
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/* TMC_FFCR - 0x304 */
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#define TMC_FFCR_EN_FMT BIT(0)
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#define TMC_FFCR_EN_TI BIT(1)
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#define TMC_FFCR_FON_FLIN BIT(4)
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#define TMC_FFCR_FON_TRIG_EVT BIT(5)
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#define TMC_FFCR_FLUSHMAN BIT(6)
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#define TMC_FFCR_TRIGON_TRIGIN BIT(8)
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#define TMC_FFCR_STOP_ON_FLUSH BIT(12)
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#define TMC_STS_TRIGGERED_BIT 2
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#define TMC_FFCR_FLUSHMAN_BIT 6
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enum tmc_config_type {
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TMC_CONFIG_TYPE_ETB,
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TMC_CONFIG_TYPE_ETR,
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TMC_CONFIG_TYPE_ETF,
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};
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enum tmc_mode {
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TMC_MODE_CIRCULAR_BUFFER,
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TMC_MODE_SOFTWARE_FIFO,
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TMC_MODE_HARDWARE_FIFO,
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};
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enum tmc_mem_intf_width {
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TMC_MEM_INTF_WIDTH_32BITS = 0x2,
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TMC_MEM_INTF_WIDTH_64BITS = 0x3,
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TMC_MEM_INTF_WIDTH_128BITS = 0x4,
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TMC_MEM_INTF_WIDTH_256BITS = 0x5,
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};
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/**
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* struct tmc_drvdata - specifics associated to an TMC component
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* @base: memory mapped base address for this component.
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* @dev: the device entity associated to this component.
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* @csdev: component vitals needed by the framework.
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* @miscdev: specifics to handle "/dev/xyz.tmc" entry.
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* @clk: the clock this component is associated to.
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* @spinlock: only one at a time pls.
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* @read_count: manages preparation of buffer for reading.
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* @buf: area of memory where trace data get sent.
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* @paddr: DMA start location in RAM.
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* @vaddr: virtual representation of @paddr.
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* @size: @buf size.
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* @enable: this TMC is being used.
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* @config_type: TMC variant, must be of type @tmc_config_type.
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* @trigger_cntr: amount of words to store after a trigger.
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*/
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struct tmc_drvdata {
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void __iomem *base;
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struct device *dev;
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struct coresight_device *csdev;
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struct miscdevice miscdev;
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struct clk *clk;
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spinlock_t spinlock;
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int read_count;
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bool reading;
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char *buf;
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dma_addr_t paddr;
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void __iomem *vaddr;
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u32 size;
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bool enable;
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enum tmc_config_type config_type;
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u32 trigger_cntr;
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};
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static void tmc_wait_for_ready(struct tmc_drvdata *drvdata)
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{
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/* Ensure formatter, unformatter and hardware fifo are empty */
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if (coresight_timeout(drvdata->base,
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TMC_STS, TMC_STS_TRIGGERED_BIT, 1)) {
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dev_err(drvdata->dev,
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"timeout observed when probing at offset %#x\n",
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TMC_STS);
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}
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}
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static void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
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{
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u32 ffcr;
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ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
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ffcr |= TMC_FFCR_STOP_ON_FLUSH;
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writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
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ffcr |= TMC_FFCR_FLUSHMAN;
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writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
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/* Ensure flush completes */
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if (coresight_timeout(drvdata->base,
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TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
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dev_err(drvdata->dev,
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"timeout observed when probing at offset %#x\n",
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TMC_FFCR);
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}
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tmc_wait_for_ready(drvdata);
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}
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static void tmc_enable_hw(struct tmc_drvdata *drvdata)
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{
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writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
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}
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static void tmc_disable_hw(struct tmc_drvdata *drvdata)
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{
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writel_relaxed(0x0, drvdata->base + TMC_CTL);
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}
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static void tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
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{
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/* Zero out the memory to help with debug */
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memset(drvdata->buf, 0, drvdata->size);
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CS_UNLOCK(drvdata->base);
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writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
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writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
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TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
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TMC_FFCR_TRIGON_TRIGIN,
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drvdata->base + TMC_FFCR);
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writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
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tmc_enable_hw(drvdata);
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CS_LOCK(drvdata->base);
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}
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static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
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{
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u32 axictl;
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/* Zero out the memory to help with debug */
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memset(drvdata->vaddr, 0, drvdata->size);
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CS_UNLOCK(drvdata->base);
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writel_relaxed(drvdata->size / 4, drvdata->base + TMC_RSZ);
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writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
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axictl = readl_relaxed(drvdata->base + TMC_AXICTL);
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axictl |= TMC_AXICTL_WR_BURST_LEN;
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writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
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axictl &= ~TMC_AXICTL_SCT_GAT_MODE;
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writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
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axictl = (axictl &
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~(TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1)) |
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TMC_AXICTL_PROT_CTL_B1;
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writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
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writel_relaxed(drvdata->paddr, drvdata->base + TMC_DBALO);
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writel_relaxed(0x0, drvdata->base + TMC_DBAHI);
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writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
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TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
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TMC_FFCR_TRIGON_TRIGIN,
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drvdata->base + TMC_FFCR);
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writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
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tmc_enable_hw(drvdata);
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CS_LOCK(drvdata->base);
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}
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static void tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
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{
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CS_UNLOCK(drvdata->base);
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writel_relaxed(TMC_MODE_HARDWARE_FIFO, drvdata->base + TMC_MODE);
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writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI,
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drvdata->base + TMC_FFCR);
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writel_relaxed(0x0, drvdata->base + TMC_BUFWM);
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tmc_enable_hw(drvdata);
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CS_LOCK(drvdata->base);
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}
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static int tmc_enable(struct tmc_drvdata *drvdata, enum tmc_mode mode)
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{
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int ret;
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unsigned long flags;
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ret = clk_prepare_enable(drvdata->clk);
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if (ret)
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return ret;
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spin_lock_irqsave(&drvdata->spinlock, flags);
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if (drvdata->reading) {
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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clk_disable_unprepare(drvdata->clk);
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return -EBUSY;
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}
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if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
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tmc_etb_enable_hw(drvdata);
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} else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
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tmc_etr_enable_hw(drvdata);
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} else {
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if (mode == TMC_MODE_CIRCULAR_BUFFER)
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tmc_etb_enable_hw(drvdata);
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else
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tmc_etf_enable_hw(drvdata);
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}
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drvdata->enable = true;
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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dev_info(drvdata->dev, "TMC enabled\n");
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return 0;
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}
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static int tmc_enable_sink(struct coresight_device *csdev)
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{
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struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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return tmc_enable(drvdata, TMC_MODE_CIRCULAR_BUFFER);
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}
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static int tmc_enable_link(struct coresight_device *csdev, int inport,
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int outport)
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{
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struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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return tmc_enable(drvdata, TMC_MODE_HARDWARE_FIFO);
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}
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static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
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{
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enum tmc_mem_intf_width memwidth;
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u8 memwords;
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char *bufp;
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u32 read_data;
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int i;
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memwidth = BMVAL(readl_relaxed(drvdata->base + CORESIGHT_DEVID), 8, 10);
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if (memwidth == TMC_MEM_INTF_WIDTH_32BITS)
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memwords = 1;
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else if (memwidth == TMC_MEM_INTF_WIDTH_64BITS)
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memwords = 2;
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else if (memwidth == TMC_MEM_INTF_WIDTH_128BITS)
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memwords = 4;
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else
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memwords = 8;
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bufp = drvdata->buf;
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while (1) {
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for (i = 0; i < memwords; i++) {
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read_data = readl_relaxed(drvdata->base + TMC_RRD);
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if (read_data == 0xFFFFFFFF)
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return;
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memcpy(bufp, &read_data, 4);
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bufp += 4;
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}
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}
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}
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static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
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{
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CS_UNLOCK(drvdata->base);
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tmc_flush_and_stop(drvdata);
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tmc_etb_dump_hw(drvdata);
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tmc_disable_hw(drvdata);
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CS_LOCK(drvdata->base);
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}
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static void tmc_etr_dump_hw(struct tmc_drvdata *drvdata)
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{
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u32 rwp, val;
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rwp = readl_relaxed(drvdata->base + TMC_RWP);
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val = readl_relaxed(drvdata->base + TMC_STS);
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/* How much memory do we still have */
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if (val & BIT(0))
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drvdata->buf = drvdata->vaddr + rwp - drvdata->paddr;
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else
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drvdata->buf = drvdata->vaddr;
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}
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static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
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{
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CS_UNLOCK(drvdata->base);
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tmc_flush_and_stop(drvdata);
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tmc_etr_dump_hw(drvdata);
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tmc_disable_hw(drvdata);
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CS_LOCK(drvdata->base);
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}
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static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata)
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{
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CS_UNLOCK(drvdata->base);
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tmc_flush_and_stop(drvdata);
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tmc_disable_hw(drvdata);
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CS_LOCK(drvdata->base);
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}
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static void tmc_disable(struct tmc_drvdata *drvdata, enum tmc_mode mode)
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{
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unsigned long flags;
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spin_lock_irqsave(&drvdata->spinlock, flags);
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if (drvdata->reading)
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goto out;
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if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
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tmc_etb_disable_hw(drvdata);
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} else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
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tmc_etr_disable_hw(drvdata);
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} else {
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if (mode == TMC_MODE_CIRCULAR_BUFFER)
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tmc_etb_disable_hw(drvdata);
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else
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tmc_etf_disable_hw(drvdata);
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}
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out:
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drvdata->enable = false;
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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clk_disable_unprepare(drvdata->clk);
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dev_info(drvdata->dev, "TMC disabled\n");
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}
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static void tmc_disable_sink(struct coresight_device *csdev)
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{
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struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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tmc_disable(drvdata, TMC_MODE_CIRCULAR_BUFFER);
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}
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static void tmc_disable_link(struct coresight_device *csdev, int inport,
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int outport)
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{
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struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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tmc_disable(drvdata, TMC_MODE_HARDWARE_FIFO);
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}
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static const struct coresight_ops_sink tmc_sink_ops = {
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.enable = tmc_enable_sink,
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.disable = tmc_disable_sink,
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};
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static const struct coresight_ops_link tmc_link_ops = {
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.enable = tmc_enable_link,
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.disable = tmc_disable_link,
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};
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static const struct coresight_ops tmc_etb_cs_ops = {
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.sink_ops = &tmc_sink_ops,
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};
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static const struct coresight_ops tmc_etr_cs_ops = {
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.sink_ops = &tmc_sink_ops,
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};
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static const struct coresight_ops tmc_etf_cs_ops = {
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.sink_ops = &tmc_sink_ops,
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.link_ops = &tmc_link_ops,
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};
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static int tmc_read_prepare(struct tmc_drvdata *drvdata)
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{
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int ret;
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unsigned long flags;
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enum tmc_mode mode;
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spin_lock_irqsave(&drvdata->spinlock, flags);
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if (!drvdata->enable)
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goto out;
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if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
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tmc_etb_disable_hw(drvdata);
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} else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
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tmc_etr_disable_hw(drvdata);
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} else {
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mode = readl_relaxed(drvdata->base + TMC_MODE);
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if (mode == TMC_MODE_CIRCULAR_BUFFER) {
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tmc_etb_disable_hw(drvdata);
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} else {
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ret = -ENODEV;
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goto err;
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}
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}
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out:
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drvdata->reading = true;
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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dev_info(drvdata->dev, "TMC read start\n");
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return 0;
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err:
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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return ret;
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}
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|
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static void tmc_read_unprepare(struct tmc_drvdata *drvdata)
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{
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unsigned long flags;
|
|
enum tmc_mode mode;
|
|
|
|
spin_lock_irqsave(&drvdata->spinlock, flags);
|
|
if (!drvdata->enable)
|
|
goto out;
|
|
|
|
if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
|
|
tmc_etb_enable_hw(drvdata);
|
|
} else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
|
|
tmc_etr_enable_hw(drvdata);
|
|
} else {
|
|
mode = readl_relaxed(drvdata->base + TMC_MODE);
|
|
if (mode == TMC_MODE_CIRCULAR_BUFFER)
|
|
tmc_etb_enable_hw(drvdata);
|
|
}
|
|
out:
|
|
drvdata->reading = false;
|
|
spin_unlock_irqrestore(&drvdata->spinlock, flags);
|
|
|
|
dev_info(drvdata->dev, "TMC read end\n");
|
|
}
|
|
|
|
static int tmc_open(struct inode *inode, struct file *file)
|
|
{
|
|
struct tmc_drvdata *drvdata = container_of(file->private_data,
|
|
struct tmc_drvdata, miscdev);
|
|
int ret = 0;
|
|
|
|
if (drvdata->read_count++)
|
|
goto out;
|
|
|
|
ret = tmc_read_prepare(drvdata);
|
|
if (ret)
|
|
return ret;
|
|
out:
|
|
nonseekable_open(inode, file);
|
|
|
|
dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
|
|
loff_t *ppos)
|
|
{
|
|
struct tmc_drvdata *drvdata = container_of(file->private_data,
|
|
struct tmc_drvdata, miscdev);
|
|
char *bufp = drvdata->buf + *ppos;
|
|
|
|
if (*ppos + len > drvdata->size)
|
|
len = drvdata->size - *ppos;
|
|
|
|
if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
|
|
if (bufp == (char *)(drvdata->vaddr + drvdata->size))
|
|
bufp = drvdata->vaddr;
|
|
else if (bufp > (char *)(drvdata->vaddr + drvdata->size))
|
|
bufp -= drvdata->size;
|
|
if ((bufp + len) > (char *)(drvdata->vaddr + drvdata->size))
|
|
len = (char *)(drvdata->vaddr + drvdata->size) - bufp;
|
|
}
|
|
|
|
if (copy_to_user(data, bufp, len)) {
|
|
dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
|
|
return -EFAULT;
|
|
}
|
|
|
|
*ppos += len;
|
|
|
|
dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n",
|
|
__func__, len, (int)(drvdata->size - *ppos));
|
|
return len;
|
|
}
|
|
|
|
static int tmc_release(struct inode *inode, struct file *file)
|
|
{
|
|
struct tmc_drvdata *drvdata = container_of(file->private_data,
|
|
struct tmc_drvdata, miscdev);
|
|
|
|
if (--drvdata->read_count) {
|
|
if (drvdata->read_count < 0) {
|
|
dev_err(drvdata->dev, "mismatched close\n");
|
|
drvdata->read_count = 0;
|
|
}
|
|
goto out;
|
|
}
|
|
|
|
tmc_read_unprepare(drvdata);
|
|
out:
|
|
dev_dbg(drvdata->dev, "%s: released\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
static const struct file_operations tmc_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = tmc_open,
|
|
.read = tmc_read,
|
|
.release = tmc_release,
|
|
.llseek = no_llseek,
|
|
};
|
|
|
|
static ssize_t status_show(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret;
|
|
unsigned long flags;
|
|
u32 tmc_rsz, tmc_sts, tmc_rrp, tmc_rwp, tmc_trg;
|
|
u32 tmc_ctl, tmc_ffsr, tmc_ffcr, tmc_mode, tmc_pscr;
|
|
u32 devid;
|
|
struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
|
|
|
ret = clk_prepare_enable(drvdata->clk);
|
|
if (ret)
|
|
goto out;
|
|
|
|
spin_lock_irqsave(&drvdata->spinlock, flags);
|
|
CS_UNLOCK(drvdata->base);
|
|
|
|
tmc_rsz = readl_relaxed(drvdata->base + TMC_RSZ);
|
|
tmc_sts = readl_relaxed(drvdata->base + TMC_STS);
|
|
tmc_rrp = readl_relaxed(drvdata->base + TMC_RRP);
|
|
tmc_rwp = readl_relaxed(drvdata->base + TMC_RWP);
|
|
tmc_trg = readl_relaxed(drvdata->base + TMC_TRG);
|
|
tmc_ctl = readl_relaxed(drvdata->base + TMC_CTL);
|
|
tmc_ffsr = readl_relaxed(drvdata->base + TMC_FFSR);
|
|
tmc_ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
|
|
tmc_mode = readl_relaxed(drvdata->base + TMC_MODE);
|
|
tmc_pscr = readl_relaxed(drvdata->base + TMC_PSCR);
|
|
devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
|
|
|
|
CS_LOCK(drvdata->base);
|
|
spin_unlock_irqrestore(&drvdata->spinlock, flags);
|
|
|
|
clk_disable_unprepare(drvdata->clk);
|
|
|
|
return sprintf(buf,
|
|
"Depth:\t\t0x%x\n"
|
|
"Status:\t\t0x%x\n"
|
|
"RAM read ptr:\t0x%x\n"
|
|
"RAM wrt ptr:\t0x%x\n"
|
|
"Trigger cnt:\t0x%x\n"
|
|
"Control:\t0x%x\n"
|
|
"Flush status:\t0x%x\n"
|
|
"Flush ctrl:\t0x%x\n"
|
|
"Mode:\t\t0x%x\n"
|
|
"PSRC:\t\t0x%x\n"
|
|
"DEVID:\t\t0x%x\n",
|
|
tmc_rsz, tmc_sts, tmc_rrp, tmc_rwp, tmc_trg,
|
|
tmc_ctl, tmc_ffsr, tmc_ffcr, tmc_mode, tmc_pscr, devid);
|
|
out:
|
|
return -EINVAL;
|
|
}
|
|
static DEVICE_ATTR_RO(status);
|
|
|
|
static ssize_t trigger_cntr_show(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
|
unsigned long val = drvdata->trigger_cntr;
|
|
|
|
return sprintf(buf, "%#lx\n", val);
|
|
}
|
|
|
|
static ssize_t trigger_cntr_store(struct device *dev,
|
|
struct device_attribute *attr,
|
|
const char *buf, size_t size)
|
|
{
|
|
int ret;
|
|
unsigned long val;
|
|
struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
|
|
|
ret = kstrtoul(buf, 16, &val);
|
|
if (ret)
|
|
return ret;
|
|
|
|
drvdata->trigger_cntr = val;
|
|
return size;
|
|
}
|
|
static DEVICE_ATTR_RW(trigger_cntr);
|
|
|
|
static struct attribute *coresight_etb_attrs[] = {
|
|
&dev_attr_trigger_cntr.attr,
|
|
&dev_attr_status.attr,
|
|
NULL,
|
|
};
|
|
ATTRIBUTE_GROUPS(coresight_etb);
|
|
|
|
static struct attribute *coresight_etr_attrs[] = {
|
|
&dev_attr_trigger_cntr.attr,
|
|
&dev_attr_status.attr,
|
|
NULL,
|
|
};
|
|
ATTRIBUTE_GROUPS(coresight_etr);
|
|
|
|
static struct attribute *coresight_etf_attrs[] = {
|
|
&dev_attr_trigger_cntr.attr,
|
|
&dev_attr_status.attr,
|
|
NULL,
|
|
};
|
|
ATTRIBUTE_GROUPS(coresight_etf);
|
|
|
|
static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
|
|
{
|
|
int ret = 0;
|
|
u32 devid;
|
|
void __iomem *base;
|
|
struct device *dev = &adev->dev;
|
|
struct coresight_platform_data *pdata = NULL;
|
|
struct tmc_drvdata *drvdata;
|
|
struct resource *res = &adev->res;
|
|
struct coresight_desc *desc;
|
|
struct device_node *np = adev->dev.of_node;
|
|
|
|
if (np) {
|
|
pdata = of_get_coresight_platform_data(dev, np);
|
|
if (IS_ERR(pdata))
|
|
return PTR_ERR(pdata);
|
|
adev->dev.platform_data = pdata;
|
|
}
|
|
|
|
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
|
|
if (!drvdata)
|
|
return -ENOMEM;
|
|
|
|
drvdata->dev = &adev->dev;
|
|
dev_set_drvdata(dev, drvdata);
|
|
|
|
/* Validity for the resource is already checked by the AMBA core */
|
|
base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
drvdata->base = base;
|
|
|
|
spin_lock_init(&drvdata->spinlock);
|
|
|
|
drvdata->clk = adev->pclk;
|
|
ret = clk_prepare_enable(drvdata->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
|
|
drvdata->config_type = BMVAL(devid, 6, 7);
|
|
|
|
if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
|
|
if (np)
|
|
ret = of_property_read_u32(np,
|
|
"arm,buffer-size",
|
|
&drvdata->size);
|
|
if (ret)
|
|
drvdata->size = SZ_1M;
|
|
} else {
|
|
drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
|
|
}
|
|
|
|
clk_disable_unprepare(drvdata->clk);
|
|
|
|
if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
|
|
drvdata->vaddr = dma_alloc_coherent(dev, drvdata->size,
|
|
&drvdata->paddr, GFP_KERNEL);
|
|
if (!drvdata->vaddr)
|
|
return -ENOMEM;
|
|
|
|
memset(drvdata->vaddr, 0, drvdata->size);
|
|
drvdata->buf = drvdata->vaddr;
|
|
} else {
|
|
drvdata->buf = devm_kzalloc(dev, drvdata->size, GFP_KERNEL);
|
|
if (!drvdata->buf)
|
|
return -ENOMEM;
|
|
}
|
|
|
|
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
|
|
if (!desc) {
|
|
ret = -ENOMEM;
|
|
goto err_devm_kzalloc;
|
|
}
|
|
|
|
desc->pdata = pdata;
|
|
desc->dev = dev;
|
|
desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
|
|
|
|
if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
|
|
desc->type = CORESIGHT_DEV_TYPE_SINK;
|
|
desc->ops = &tmc_etb_cs_ops;
|
|
desc->groups = coresight_etb_groups;
|
|
} else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
|
|
desc->type = CORESIGHT_DEV_TYPE_SINK;
|
|
desc->ops = &tmc_etr_cs_ops;
|
|
desc->groups = coresight_etr_groups;
|
|
} else {
|
|
desc->type = CORESIGHT_DEV_TYPE_LINKSINK;
|
|
desc->subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
|
|
desc->ops = &tmc_etf_cs_ops;
|
|
desc->groups = coresight_etf_groups;
|
|
}
|
|
|
|
drvdata->csdev = coresight_register(desc);
|
|
if (IS_ERR(drvdata->csdev)) {
|
|
ret = PTR_ERR(drvdata->csdev);
|
|
goto err_devm_kzalloc;
|
|
}
|
|
|
|
drvdata->miscdev.name = pdata->name;
|
|
drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
|
|
drvdata->miscdev.fops = &tmc_fops;
|
|
ret = misc_register(&drvdata->miscdev);
|
|
if (ret)
|
|
goto err_misc_register;
|
|
|
|
dev_info(dev, "TMC initialized\n");
|
|
return 0;
|
|
|
|
err_misc_register:
|
|
coresight_unregister(drvdata->csdev);
|
|
err_devm_kzalloc:
|
|
if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
|
|
dma_free_coherent(dev, drvdata->size,
|
|
&drvdata->paddr, GFP_KERNEL);
|
|
return ret;
|
|
}
|
|
|
|
static int tmc_remove(struct amba_device *adev)
|
|
{
|
|
struct tmc_drvdata *drvdata = amba_get_drvdata(adev);
|
|
|
|
misc_deregister(&drvdata->miscdev);
|
|
coresight_unregister(drvdata->csdev);
|
|
if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
|
|
dma_free_coherent(drvdata->dev, drvdata->size,
|
|
&drvdata->paddr, GFP_KERNEL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct amba_id tmc_ids[] = {
|
|
{
|
|
.id = 0x0003b961,
|
|
.mask = 0x0003ffff,
|
|
},
|
|
{ 0, 0},
|
|
};
|
|
|
|
static struct amba_driver tmc_driver = {
|
|
.drv = {
|
|
.name = "coresight-tmc",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.probe = tmc_probe,
|
|
.remove = tmc_remove,
|
|
.id_table = tmc_ids,
|
|
};
|
|
|
|
module_amba_driver(tmc_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("CoreSight Trace Memory Controller driver");
|