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synced 2024-08-27 11:19:37 +00:00
![Linus Torvalds](/assets/img/avatar_default.png)
Here's the big set of USB and PHY patches for 3.19-rc1. The normal churn in the USB gadget area is in here, as well as xhci and other individual USB driver updates. The PHY tree is also in here, as there were dependancies on the USB tree. All of these have been in linux-next. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEABECAAYFAlSOEHcACgkQMUfUDdst+ykziQCgsm1D/af2nac6CTF2pov8VMIY ywgAnRi8LtZ2WassrwTNxY86Avaqryis =UVp8 -----END PGP SIGNATURE----- Merge tag 'usb-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB updates from Greg KH: "Here's the big set of USB and PHY patches for 3.19-rc1. The normal churn in the USB gadget area is in here, as well as xhci and other individual USB driver updates. The PHY tree is also in here, as there were dependancies on the USB tree. All of these have been in linux-next" * tag 'usb-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (351 commits) arm: omap3: twl: remove usb phy init data usbip: fix error handling in stub_probe() usb: gadget: udc: missing curly braces USB: mos7720: delete some unneeded code wusb: replace memset by memzero_explicit usbip: remove unneeded structure usb: xhci: fix comment for PORT_DEV_REMOVE xhci: don't use the same variable for stopped and halted rings current TD xhci: clear extra bits from slot context when setting max exit latency xhci: cleanup finish_td function USB: adutux: NULL dereferences on disconnect usb: chipidea: fix platform_no_drv_owner.cocci warnings usb: chipidea: Fixed a few typos in comments Documentation: bindings: add doc for the USB2 ChipIdea USB driver usb: chipidea: add a usb2 driver for ci13xxx usb: chipidea: fix phy handling usb: chipidea: remove duplicate dev_set_drvdata for host_start usb: chipidea: parameter 'mode' isn't needed for hw_device_reset usb: chipidea: add controller reset API usb: chipidea: remove flag CI_HDRC_REQUIRE_TRANSCEIVER ...
979 lines
24 KiB
C
979 lines
24 KiB
C
/*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
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#include "core.h"
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#include "pinctrl-utils.h"
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#define XUSB_PADCTL_ELPG_PROGRAM 0x01c
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#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
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#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
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#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
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struct tegra_xusb_padctl_function {
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const char *name;
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const char * const *groups;
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unsigned int num_groups;
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};
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struct tegra_xusb_padctl_group {
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const unsigned int *funcs;
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unsigned int num_funcs;
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};
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struct tegra_xusb_padctl_soc {
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const struct pinctrl_pin_desc *pins;
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unsigned int num_pins;
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const struct tegra_xusb_padctl_function *functions;
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unsigned int num_functions;
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const struct tegra_xusb_padctl_lane *lanes;
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unsigned int num_lanes;
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};
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struct tegra_xusb_padctl_lane {
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const char *name;
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unsigned int offset;
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unsigned int shift;
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unsigned int mask;
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unsigned int iddq;
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const unsigned int *funcs;
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unsigned int num_funcs;
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};
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struct tegra_xusb_padctl {
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struct device *dev;
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void __iomem *regs;
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struct mutex lock;
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struct reset_control *rst;
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const struct tegra_xusb_padctl_soc *soc;
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struct pinctrl_dev *pinctrl;
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struct pinctrl_desc desc;
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struct phy_provider *provider;
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struct phy *phys[2];
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unsigned int enable;
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};
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static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
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unsigned long offset)
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{
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writel(value, padctl->regs + offset);
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}
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static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
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unsigned long offset)
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{
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return readl(padctl->regs + offset);
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}
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static int tegra_xusb_padctl_get_groups_count(struct pinctrl_dev *pinctrl)
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{
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struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
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return padctl->soc->num_pins;
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}
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static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl,
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unsigned int group)
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{
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struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
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return padctl->soc->pins[group].name;
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}
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enum tegra_xusb_padctl_param {
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TEGRA_XUSB_PADCTL_IDDQ,
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};
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static const struct tegra_xusb_padctl_property {
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const char *name;
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enum tegra_xusb_padctl_param param;
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} properties[] = {
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{ "nvidia,iddq", TEGRA_XUSB_PADCTL_IDDQ },
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};
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#define TEGRA_XUSB_PADCTL_PACK(param, value) ((param) << 16 | (value))
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#define TEGRA_XUSB_PADCTL_UNPACK_PARAM(config) ((config) >> 16)
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#define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff)
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static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl,
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struct device_node *np,
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struct pinctrl_map **maps,
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unsigned int *reserved_maps,
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unsigned int *num_maps)
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{
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unsigned int i, reserve = 0, num_configs = 0;
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unsigned long config, *configs = NULL;
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const char *function, *group;
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struct property *prop;
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int err = 0;
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u32 value;
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err = of_property_read_string(np, "nvidia,function", &function);
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if (err < 0) {
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if (err != -EINVAL)
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return err;
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function = NULL;
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}
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for (i = 0; i < ARRAY_SIZE(properties); i++) {
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err = of_property_read_u32(np, properties[i].name, &value);
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if (err < 0) {
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if (err == -EINVAL)
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continue;
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goto out;
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}
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config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, value);
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err = pinctrl_utils_add_config(padctl->pinctrl, &configs,
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&num_configs, config);
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if (err < 0)
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goto out;
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}
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if (function)
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reserve++;
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if (num_configs)
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reserve++;
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err = of_property_count_strings(np, "nvidia,lanes");
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if (err < 0)
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goto out;
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reserve *= err;
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err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps,
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num_maps, reserve);
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if (err < 0)
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goto out;
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of_property_for_each_string(np, "nvidia,lanes", prop, group) {
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if (function) {
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err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps,
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reserved_maps, num_maps, group,
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function);
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if (err < 0)
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goto out;
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}
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if (num_configs) {
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err = pinctrl_utils_add_map_configs(padctl->pinctrl,
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maps, reserved_maps, num_maps, group,
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configs, num_configs,
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PIN_MAP_TYPE_CONFIGS_GROUP);
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if (err < 0)
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goto out;
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}
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}
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err = 0;
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out:
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kfree(configs);
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return err;
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}
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static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl,
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struct device_node *parent,
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struct pinctrl_map **maps,
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unsigned int *num_maps)
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{
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struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
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unsigned int reserved_maps = 0;
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struct device_node *np;
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int err;
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*num_maps = 0;
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*maps = NULL;
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for_each_child_of_node(parent, np) {
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err = tegra_xusb_padctl_parse_subnode(padctl, np, maps,
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&reserved_maps,
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num_maps);
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if (err < 0)
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return err;
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}
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return 0;
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}
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static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = {
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.get_groups_count = tegra_xusb_padctl_get_groups_count,
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.get_group_name = tegra_xusb_padctl_get_group_name,
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.dt_node_to_map = tegra_xusb_padctl_dt_node_to_map,
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.dt_free_map = pinctrl_utils_dt_free_map,
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};
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static int tegra_xusb_padctl_get_functions_count(struct pinctrl_dev *pinctrl)
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{
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struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
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return padctl->soc->num_functions;
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}
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static const char *
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tegra_xusb_padctl_get_function_name(struct pinctrl_dev *pinctrl,
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unsigned int function)
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{
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struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
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return padctl->soc->functions[function].name;
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}
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static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl,
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unsigned int function,
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const char * const **groups,
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unsigned * const num_groups)
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{
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struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
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*num_groups = padctl->soc->functions[function].num_groups;
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*groups = padctl->soc->functions[function].groups;
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return 0;
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}
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static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl,
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unsigned int function,
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unsigned int group)
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{
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struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
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const struct tegra_xusb_padctl_lane *lane;
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unsigned int i;
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u32 value;
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lane = &padctl->soc->lanes[group];
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for (i = 0; i < lane->num_funcs; i++)
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if (lane->funcs[i] == function)
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break;
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if (i >= lane->num_funcs)
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return -EINVAL;
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value = padctl_readl(padctl, lane->offset);
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value &= ~(lane->mask << lane->shift);
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value |= i << lane->shift;
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padctl_writel(padctl, value, lane->offset);
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return 0;
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}
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static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = {
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.get_functions_count = tegra_xusb_padctl_get_functions_count,
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.get_function_name = tegra_xusb_padctl_get_function_name,
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.get_function_groups = tegra_xusb_padctl_get_function_groups,
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.set_mux = tegra_xusb_padctl_pinmux_set,
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};
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static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl,
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unsigned int group,
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unsigned long *config)
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{
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struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
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const struct tegra_xusb_padctl_lane *lane;
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enum tegra_xusb_padctl_param param;
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u32 value;
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param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(*config);
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lane = &padctl->soc->lanes[group];
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switch (param) {
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case TEGRA_XUSB_PADCTL_IDDQ:
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/* lanes with iddq == 0 don't support this parameter */
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if (lane->iddq == 0)
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return -EINVAL;
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value = padctl_readl(padctl, lane->offset);
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if (value & BIT(lane->iddq))
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value = 0;
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else
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value = 1;
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*config = TEGRA_XUSB_PADCTL_PACK(param, value);
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break;
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default:
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dev_err(padctl->dev, "invalid configuration parameter: %04x\n",
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param);
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return -ENOTSUPP;
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}
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return 0;
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}
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static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl,
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unsigned int group,
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unsigned long *configs,
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unsigned int num_configs)
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{
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struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
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const struct tegra_xusb_padctl_lane *lane;
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enum tegra_xusb_padctl_param param;
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unsigned long value;
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unsigned int i;
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u32 regval;
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lane = &padctl->soc->lanes[group];
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for (i = 0; i < num_configs; i++) {
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param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(configs[i]);
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value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(configs[i]);
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switch (param) {
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case TEGRA_XUSB_PADCTL_IDDQ:
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/* lanes with iddq == 0 don't support this parameter */
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if (lane->iddq == 0)
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return -EINVAL;
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regval = padctl_readl(padctl, lane->offset);
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if (value)
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regval &= ~BIT(lane->iddq);
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else
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regval |= BIT(lane->iddq);
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padctl_writel(padctl, regval, lane->offset);
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break;
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default:
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dev_err(padctl->dev,
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"invalid configuration parameter: %04x\n",
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param);
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return -ENOTSUPP;
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}
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}
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return 0;
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}
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#ifdef CONFIG_DEBUG_FS
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static const char *strip_prefix(const char *s)
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{
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const char *comma = strchr(s, ',');
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if (!comma)
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return s;
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return comma + 1;
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}
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static void
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tegra_xusb_padctl_pinconf_group_dbg_show(struct pinctrl_dev *pinctrl,
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struct seq_file *s,
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unsigned int group)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(properties); i++) {
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unsigned long config, value;
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int err;
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config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, 0);
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|
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err = tegra_xusb_padctl_pinconf_group_get(pinctrl, group,
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&config);
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if (err < 0)
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continue;
|
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|
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value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
|
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|
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seq_printf(s, "\n\t%s=%lu\n", strip_prefix(properties[i].name),
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value);
|
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}
|
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}
|
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|
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static void
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tegra_xusb_padctl_pinconf_config_dbg_show(struct pinctrl_dev *pinctrl,
|
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struct seq_file *s,
|
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unsigned long config)
|
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{
|
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enum tegra_xusb_padctl_param param;
|
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const char *name = "unknown";
|
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unsigned long value;
|
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unsigned int i;
|
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|
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param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(config);
|
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value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
|
|
|
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for (i = 0; i < ARRAY_SIZE(properties); i++) {
|
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if (properties[i].param == param) {
|
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name = properties[i].name;
|
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break;
|
|
}
|
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}
|
|
|
|
seq_printf(s, "%s=%lu", strip_prefix(name), value);
|
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}
|
|
#endif
|
|
|
|
static const struct pinconf_ops tegra_xusb_padctl_pinconf_ops = {
|
|
.pin_config_group_get = tegra_xusb_padctl_pinconf_group_get,
|
|
.pin_config_group_set = tegra_xusb_padctl_pinconf_group_set,
|
|
#ifdef CONFIG_DEBUG_FS
|
|
.pin_config_group_dbg_show = tegra_xusb_padctl_pinconf_group_dbg_show,
|
|
.pin_config_config_dbg_show = tegra_xusb_padctl_pinconf_config_dbg_show,
|
|
#endif
|
|
};
|
|
|
|
static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
|
|
{
|
|
u32 value;
|
|
|
|
mutex_lock(&padctl->lock);
|
|
|
|
if (padctl->enable++ > 0)
|
|
goto out;
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
|
|
value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
|
|
|
|
usleep_range(100, 200);
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
|
|
value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
|
|
|
|
usleep_range(100, 200);
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
|
|
value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
|
|
|
|
out:
|
|
mutex_unlock(&padctl->lock);
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
|
|
{
|
|
u32 value;
|
|
|
|
mutex_lock(&padctl->lock);
|
|
|
|
if (WARN_ON(padctl->enable == 0))
|
|
goto out;
|
|
|
|
if (--padctl->enable > 0)
|
|
goto out;
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
|
|
value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
|
|
|
|
usleep_range(100, 200);
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
|
|
value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
|
|
|
|
usleep_range(100, 200);
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
|
|
value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
|
|
|
|
out:
|
|
mutex_unlock(&padctl->lock);
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_xusb_phy_init(struct phy *phy)
|
|
{
|
|
struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
|
|
|
|
return tegra_xusb_padctl_enable(padctl);
|
|
}
|
|
|
|
static int tegra_xusb_phy_exit(struct phy *phy)
|
|
{
|
|
struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
|
|
|
|
return tegra_xusb_padctl_disable(padctl);
|
|
}
|
|
|
|
static int pcie_phy_power_on(struct phy *phy)
|
|
{
|
|
struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
|
|
unsigned long timeout;
|
|
int err = -ETIMEDOUT;
|
|
u32 value;
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
|
|
value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
|
|
value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
|
|
XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
|
|
XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
|
|
value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
|
|
|
|
timeout = jiffies + msecs_to_jiffies(50);
|
|
|
|
while (time_before(jiffies, timeout)) {
|
|
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
|
|
if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
|
|
err = 0;
|
|
break;
|
|
}
|
|
|
|
usleep_range(100, 200);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static int pcie_phy_power_off(struct phy *phy)
|
|
{
|
|
struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
|
|
u32 value;
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
|
|
value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct phy_ops pcie_phy_ops = {
|
|
.init = tegra_xusb_phy_init,
|
|
.exit = tegra_xusb_phy_exit,
|
|
.power_on = pcie_phy_power_on,
|
|
.power_off = pcie_phy_power_off,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static int sata_phy_power_on(struct phy *phy)
|
|
{
|
|
struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
|
|
unsigned long timeout;
|
|
int err = -ETIMEDOUT;
|
|
u32 value;
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
|
|
value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
|
|
value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
|
|
value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
|
|
value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
|
|
value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
|
|
value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
|
|
|
|
timeout = jiffies + msecs_to_jiffies(50);
|
|
|
|
while (time_before(jiffies, timeout)) {
|
|
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
|
|
if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
|
|
err = 0;
|
|
break;
|
|
}
|
|
|
|
usleep_range(100, 200);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static int sata_phy_power_off(struct phy *phy)
|
|
{
|
|
struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
|
|
u32 value;
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
|
|
value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
|
|
value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
|
|
value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
|
|
value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
|
|
|
|
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
|
|
value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
|
|
value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
|
|
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct phy_ops sata_phy_ops = {
|
|
.init = tegra_xusb_phy_init,
|
|
.exit = tegra_xusb_phy_exit,
|
|
.power_on = sata_phy_power_on,
|
|
.power_off = sata_phy_power_off,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static struct phy *tegra_xusb_padctl_xlate(struct device *dev,
|
|
struct of_phandle_args *args)
|
|
{
|
|
struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev);
|
|
unsigned int index = args->args[0];
|
|
|
|
if (args->args_count <= 0)
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
if (index >= ARRAY_SIZE(padctl->phys))
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
return padctl->phys[index];
|
|
}
|
|
|
|
#define PIN_OTG_0 0
|
|
#define PIN_OTG_1 1
|
|
#define PIN_OTG_2 2
|
|
#define PIN_ULPI_0 3
|
|
#define PIN_HSIC_0 4
|
|
#define PIN_HSIC_1 5
|
|
#define PIN_PCIE_0 6
|
|
#define PIN_PCIE_1 7
|
|
#define PIN_PCIE_2 8
|
|
#define PIN_PCIE_3 9
|
|
#define PIN_PCIE_4 10
|
|
#define PIN_SATA_0 11
|
|
|
|
static const struct pinctrl_pin_desc tegra124_pins[] = {
|
|
PINCTRL_PIN(PIN_OTG_0, "otg-0"),
|
|
PINCTRL_PIN(PIN_OTG_1, "otg-1"),
|
|
PINCTRL_PIN(PIN_OTG_2, "otg-2"),
|
|
PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"),
|
|
PINCTRL_PIN(PIN_HSIC_0, "hsic-0"),
|
|
PINCTRL_PIN(PIN_HSIC_1, "hsic-1"),
|
|
PINCTRL_PIN(PIN_PCIE_0, "pcie-0"),
|
|
PINCTRL_PIN(PIN_PCIE_1, "pcie-1"),
|
|
PINCTRL_PIN(PIN_PCIE_2, "pcie-2"),
|
|
PINCTRL_PIN(PIN_PCIE_3, "pcie-3"),
|
|
PINCTRL_PIN(PIN_PCIE_4, "pcie-4"),
|
|
PINCTRL_PIN(PIN_SATA_0, "sata-0"),
|
|
};
|
|
|
|
static const char * const tegra124_snps_groups[] = {
|
|
"otg-0",
|
|
"otg-1",
|
|
"otg-2",
|
|
"ulpi-0",
|
|
"hsic-0",
|
|
"hsic-1",
|
|
};
|
|
|
|
static const char * const tegra124_xusb_groups[] = {
|
|
"otg-0",
|
|
"otg-1",
|
|
"otg-2",
|
|
"ulpi-0",
|
|
"hsic-0",
|
|
"hsic-1",
|
|
};
|
|
|
|
static const char * const tegra124_uart_groups[] = {
|
|
"otg-0",
|
|
"otg-1",
|
|
"otg-2",
|
|
};
|
|
|
|
static const char * const tegra124_pcie_groups[] = {
|
|
"pcie-0",
|
|
"pcie-1",
|
|
"pcie-2",
|
|
"pcie-3",
|
|
"pcie-4",
|
|
"sata-0",
|
|
};
|
|
|
|
static const char * const tegra124_usb3_groups[] = {
|
|
"pcie-0",
|
|
"pcie-1",
|
|
"pcie-2",
|
|
"pcie-3",
|
|
"pcie-4",
|
|
"sata-0",
|
|
};
|
|
|
|
static const char * const tegra124_sata_groups[] = {
|
|
"pcie-0",
|
|
"pcie-1",
|
|
"pcie-2",
|
|
"pcie-3",
|
|
"pcie-4",
|
|
"sata-0",
|
|
};
|
|
|
|
static const char * const tegra124_rsvd_groups[] = {
|
|
"otg-0",
|
|
"otg-1",
|
|
"otg-2",
|
|
"pcie-0",
|
|
"pcie-1",
|
|
"pcie-2",
|
|
"pcie-3",
|
|
"pcie-4",
|
|
"sata-0",
|
|
};
|
|
|
|
#define TEGRA124_FUNCTION(_name) \
|
|
{ \
|
|
.name = #_name, \
|
|
.num_groups = ARRAY_SIZE(tegra124_##_name##_groups), \
|
|
.groups = tegra124_##_name##_groups, \
|
|
}
|
|
|
|
static struct tegra_xusb_padctl_function tegra124_functions[] = {
|
|
TEGRA124_FUNCTION(snps),
|
|
TEGRA124_FUNCTION(xusb),
|
|
TEGRA124_FUNCTION(uart),
|
|
TEGRA124_FUNCTION(pcie),
|
|
TEGRA124_FUNCTION(usb3),
|
|
TEGRA124_FUNCTION(sata),
|
|
TEGRA124_FUNCTION(rsvd),
|
|
};
|
|
|
|
enum tegra124_function {
|
|
TEGRA124_FUNC_SNPS,
|
|
TEGRA124_FUNC_XUSB,
|
|
TEGRA124_FUNC_UART,
|
|
TEGRA124_FUNC_PCIE,
|
|
TEGRA124_FUNC_USB3,
|
|
TEGRA124_FUNC_SATA,
|
|
TEGRA124_FUNC_RSVD,
|
|
};
|
|
|
|
static const unsigned int tegra124_otg_functions[] = {
|
|
TEGRA124_FUNC_SNPS,
|
|
TEGRA124_FUNC_XUSB,
|
|
TEGRA124_FUNC_UART,
|
|
TEGRA124_FUNC_RSVD,
|
|
};
|
|
|
|
static const unsigned int tegra124_usb_functions[] = {
|
|
TEGRA124_FUNC_SNPS,
|
|
TEGRA124_FUNC_XUSB,
|
|
};
|
|
|
|
static const unsigned int tegra124_pci_functions[] = {
|
|
TEGRA124_FUNC_PCIE,
|
|
TEGRA124_FUNC_USB3,
|
|
TEGRA124_FUNC_SATA,
|
|
TEGRA124_FUNC_RSVD,
|
|
};
|
|
|
|
#define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
|
|
{ \
|
|
.name = _name, \
|
|
.offset = _offset, \
|
|
.shift = _shift, \
|
|
.mask = _mask, \
|
|
.iddq = _iddq, \
|
|
.num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
|
|
.funcs = tegra124_##_funcs##_functions, \
|
|
}
|
|
|
|
static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
|
|
TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
|
|
TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
|
|
TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
|
|
TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
|
|
TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
|
|
TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
|
|
TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
|
|
TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
|
|
TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
|
|
TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
|
|
TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
|
|
TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
|
|
};
|
|
|
|
static const struct tegra_xusb_padctl_soc tegra124_soc = {
|
|
.num_pins = ARRAY_SIZE(tegra124_pins),
|
|
.pins = tegra124_pins,
|
|
.num_functions = ARRAY_SIZE(tegra124_functions),
|
|
.functions = tegra124_functions,
|
|
.num_lanes = ARRAY_SIZE(tegra124_lanes),
|
|
.lanes = tegra124_lanes,
|
|
};
|
|
|
|
static const struct of_device_id tegra_xusb_padctl_of_match[] = {
|
|
{ .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, tegra_xusb_padctl_of_match);
|
|
|
|
static int tegra_xusb_padctl_probe(struct platform_device *pdev)
|
|
{
|
|
struct tegra_xusb_padctl *padctl;
|
|
const struct of_device_id *match;
|
|
struct resource *res;
|
|
struct phy *phy;
|
|
int err;
|
|
|
|
padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL);
|
|
if (!padctl)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, padctl);
|
|
mutex_init(&padctl->lock);
|
|
padctl->dev = &pdev->dev;
|
|
|
|
match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node);
|
|
padctl->soc = match->data;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
padctl->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(padctl->regs))
|
|
return PTR_ERR(padctl->regs);
|
|
|
|
padctl->rst = devm_reset_control_get(&pdev->dev, NULL);
|
|
if (IS_ERR(padctl->rst))
|
|
return PTR_ERR(padctl->rst);
|
|
|
|
err = reset_control_deassert(padctl->rst);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
memset(&padctl->desc, 0, sizeof(padctl->desc));
|
|
padctl->desc.name = dev_name(padctl->dev);
|
|
padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops;
|
|
padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops;
|
|
padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops;
|
|
padctl->desc.owner = THIS_MODULE;
|
|
|
|
padctl->pinctrl = pinctrl_register(&padctl->desc, &pdev->dev, padctl);
|
|
if (!padctl->pinctrl) {
|
|
dev_err(&pdev->dev, "failed to register pincontrol\n");
|
|
err = -ENODEV;
|
|
goto reset;
|
|
}
|
|
|
|
phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops);
|
|
if (IS_ERR(phy)) {
|
|
err = PTR_ERR(phy);
|
|
goto unregister;
|
|
}
|
|
|
|
padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy;
|
|
phy_set_drvdata(phy, padctl);
|
|
|
|
phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops);
|
|
if (IS_ERR(phy)) {
|
|
err = PTR_ERR(phy);
|
|
goto unregister;
|
|
}
|
|
|
|
padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy;
|
|
phy_set_drvdata(phy, padctl);
|
|
|
|
padctl->provider = devm_of_phy_provider_register(&pdev->dev,
|
|
tegra_xusb_padctl_xlate);
|
|
if (IS_ERR(padctl->provider)) {
|
|
err = PTR_ERR(padctl->provider);
|
|
dev_err(&pdev->dev, "failed to register PHYs: %d\n", err);
|
|
goto unregister;
|
|
}
|
|
|
|
return 0;
|
|
|
|
unregister:
|
|
pinctrl_unregister(padctl->pinctrl);
|
|
reset:
|
|
reset_control_assert(padctl->rst);
|
|
return err;
|
|
}
|
|
|
|
static int tegra_xusb_padctl_remove(struct platform_device *pdev)
|
|
{
|
|
struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev);
|
|
int err;
|
|
|
|
pinctrl_unregister(padctl->pinctrl);
|
|
|
|
err = reset_control_assert(padctl->rst);
|
|
if (err < 0)
|
|
dev_err(&pdev->dev, "failed to assert reset: %d\n", err);
|
|
|
|
return err;
|
|
}
|
|
|
|
static struct platform_driver tegra_xusb_padctl_driver = {
|
|
.driver = {
|
|
.name = "tegra-xusb-padctl",
|
|
.of_match_table = tegra_xusb_padctl_of_match,
|
|
},
|
|
.probe = tegra_xusb_padctl_probe,
|
|
.remove = tegra_xusb_padctl_remove,
|
|
};
|
|
module_platform_driver(tegra_xusb_padctl_driver);
|
|
|
|
MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
|
|
MODULE_DESCRIPTION("Tegra 124 XUSB Pad Control driver");
|
|
MODULE_LICENSE("GPL v2");
|