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![Arnd Bergmann](/assets/img/avatar_default.png)
The imx31 and imx35 idle functions are almost the same, but we currently have to check the cpu type every time. This can be simplified by moving the logic from mx3_cpu_lp_set() into two separate idle functions, removing the last user of cpu_is_mx35. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
322 lines
8.9 KiB
C
322 lines
8.9 KiB
C
/*
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* Copyright (C) 1999,2000 Arm Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* - add MX31 specific definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/pinctrl/machine.h>
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#include <asm/pgtable.h>
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#include <asm/system_misc.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/map.h>
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#include "common.h"
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#include "crmregs-imx3.h"
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#include "devices/devices-common.h"
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#include "hardware.h"
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#include "iomux-v3.h"
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void __iomem *mx3_ccm_base;
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static void imx3_idle(void)
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{
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unsigned long reg = 0;
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__asm__ __volatile__(
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/* disable I and D cache */
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"mrc p15, 0, %0, c1, c0, 0\n"
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"bic %0, %0, #0x00001000\n"
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"bic %0, %0, #0x00000004\n"
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"mcr p15, 0, %0, c1, c0, 0\n"
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/* invalidate I cache */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c5, 0\n"
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/* clear and invalidate D cache */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c14, 0\n"
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/* WFI */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c0, 4\n"
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"nop\n" "nop\n" "nop\n" "nop\n"
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"nop\n" "nop\n" "nop\n"
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/* enable I and D cache */
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"mrc p15, 0, %0, c1, c0, 0\n"
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"orr %0, %0, #0x00001000\n"
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"orr %0, %0, #0x00000004\n"
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"mcr p15, 0, %0, c1, c0, 0\n"
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: "=r" (reg));
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}
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static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
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unsigned int mtype, void *caller)
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{
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if (mtype == MT_DEVICE) {
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/*
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* Access all peripherals below 0x80000000 as nonshared device
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* on mx3, but leave l2cc alone. Otherwise cache corruptions
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* can occur.
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*/
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if (phys_addr < 0x80000000 &&
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!addr_in_module(phys_addr, MX3x_L2CC))
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mtype = MT_DEVICE_NONSHARED;
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}
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return __arm_ioremap_caller(phys_addr, size, mtype, caller);
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}
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static void __init imx3_init_l2x0(void)
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{
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *l2x0_base;
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void __iomem *clkctl_base;
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/*
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* First of all, we must repair broken chip settings. There are some
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* i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
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* misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
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* Workaraound is to setup the correct register setting prior enabling the
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* L2 cache. This should not hurt already working CPUs, as they are using the
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* same value.
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*/
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#define L2_MEM_VAL 0x10
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clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
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if (clkctl_base != NULL) {
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writel(0x00000515, clkctl_base + L2_MEM_VAL);
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iounmap(clkctl_base);
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} else {
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pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
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}
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l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
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if (!l2x0_base) {
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printk(KERN_ERR "remapping L2 cache area failed\n");
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return;
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}
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l2x0_init(l2x0_base, 0x00030024, 0x00000000);
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#endif
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}
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#ifdef CONFIG_SOC_IMX31
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static struct map_desc mx31_io_desc[] __initdata = {
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imx_map_entry(MX31, X_MEMC, MT_DEVICE),
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imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
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imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
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imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
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imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
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};
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/*
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* This function initializes the memory map. It is called during the
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* system startup to create static physical to virtual memory mappings
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* for the IO modules.
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*/
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void __init mx31_map_io(void)
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{
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iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
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}
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static void imx31_idle(void)
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{
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int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
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reg &= ~MXC_CCM_CCMR_LPM_MASK;
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imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
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imx3_idle();
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}
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void __init imx31_init_early(void)
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{
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mxc_set_cpu_type(MXC_CPU_MX31);
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arch_ioremap_caller = imx3_ioremap_caller;
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arm_pm_idle = imx31_idle;
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mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
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}
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void __init mx31_init_irq(void)
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{
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mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
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}
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static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
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.per_2_per_addr = 1677,
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};
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static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
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.ap_2_ap_addr = 423,
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.ap_2_bp_addr = 829,
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.bp_2_ap_addr = 1029,
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};
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static struct sdma_platform_data imx31_sdma_pdata __initdata = {
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.fw_name = "sdma-imx31-to2.bin",
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.script_addrs = &imx31_to2_sdma_script,
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};
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static const struct resource imx31_audmux_res[] __initconst = {
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DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
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};
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static const struct resource imx31_rnga_res[] __initconst = {
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DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K),
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};
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void __init imx31_soc_init(void)
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{
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int to_version = mx31_revision() >> 4;
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imx3_init_l2x0();
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mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
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mxc_device_init();
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mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
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mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
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mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
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pinctrl_provide_dummies();
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if (to_version == 1) {
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strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
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strlen(imx31_sdma_pdata.fw_name));
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imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
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}
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imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
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imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
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imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
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platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
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ARRAY_SIZE(imx31_audmux_res));
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platform_device_register_simple("mxc_rnga", -1, imx31_rnga_res,
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ARRAY_SIZE(imx31_rnga_res));
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}
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#endif /* ifdef CONFIG_SOC_IMX31 */
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#ifdef CONFIG_SOC_IMX35
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static struct map_desc mx35_io_desc[] __initdata = {
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imx_map_entry(MX35, X_MEMC, MT_DEVICE),
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imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
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imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
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imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
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imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
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};
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void __init mx35_map_io(void)
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{
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iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
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}
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static void imx35_idle(void)
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{
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int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
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reg &= ~MXC_CCM_CCMR_LPM_MASK;
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reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
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imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
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imx3_idle();
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}
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void __init imx35_init_early(void)
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{
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mxc_set_cpu_type(MXC_CPU_MX35);
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mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
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arm_pm_idle = imx35_idle;
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arch_ioremap_caller = imx3_ioremap_caller;
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mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
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}
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void __init mx35_init_irq(void)
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{
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mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
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}
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static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
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.ap_2_ap_addr = 642,
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.uart_2_mcu_addr = 817,
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.mcu_2_app_addr = 747,
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.uartsh_2_mcu_addr = 1183,
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.per_2_shp_addr = 1033,
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.mcu_2_shp_addr = 961,
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.ata_2_mcu_addr = 1333,
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.mcu_2_ata_addr = 1252,
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.app_2_mcu_addr = 683,
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.shp_2_per_addr = 1111,
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.shp_2_mcu_addr = 892,
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};
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static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
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.ap_2_ap_addr = 729,
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.uart_2_mcu_addr = 904,
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.per_2_app_addr = 1597,
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.mcu_2_app_addr = 834,
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.uartsh_2_mcu_addr = 1270,
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.per_2_shp_addr = 1120,
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.mcu_2_shp_addr = 1048,
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.ata_2_mcu_addr = 1429,
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.mcu_2_ata_addr = 1339,
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.app_2_per_addr = 1531,
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.app_2_mcu_addr = 770,
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.shp_2_per_addr = 1198,
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.shp_2_mcu_addr = 979,
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};
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static struct sdma_platform_data imx35_sdma_pdata __initdata = {
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.fw_name = "sdma-imx35-to2.bin",
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.script_addrs = &imx35_to2_sdma_script,
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};
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static const struct resource imx35_audmux_res[] __initconst = {
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DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K),
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};
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void __init imx35_soc_init(void)
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{
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int to_version = mx35_revision() >> 4;
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imx3_init_l2x0();
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mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
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mxc_device_init();
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mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
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mxc_register_gpio("imx35-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
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mxc_register_gpio("imx35-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
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pinctrl_provide_dummies();
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if (to_version == 1) {
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strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
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strlen(imx35_sdma_pdata.fw_name));
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imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
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}
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imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
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/* Setup AIPS registers */
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imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
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imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));
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/* i.mx35 has the i.mx31 type audmux */
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platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
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ARRAY_SIZE(imx35_audmux_res));
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}
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#endif /* ifdef CONFIG_SOC_IMX35 */
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