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![Jean-Christophe Dubois](/assets/img/avatar_default.png)
The wrong pointer is passed to the ioumap function in the cleanup path Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
646 lines
17 KiB
C
646 lines
17 KiB
C
/*
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* Copyright 2011-2014 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/genalloc.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/regmap.h>
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#include <linux/suspend.h>
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#include <asm/cacheflush.h>
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#include <asm/fncpy.h>
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#include <asm/proc-fns.h>
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#include <asm/suspend.h>
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#include <asm/tlb.h>
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#include "common.h"
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#include "hardware.h"
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#define CCR 0x0
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#define BM_CCR_WB_COUNT (0x7 << 16)
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#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
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#define BM_CCR_RBC_EN (0x1 << 27)
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#define CLPCR 0x54
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#define BP_CLPCR_LPM 0
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#define BM_CLPCR_LPM (0x3 << 0)
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#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
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#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
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#define BM_CLPCR_SBYOS (0x1 << 6)
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#define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
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#define BM_CLPCR_VSTBY (0x1 << 8)
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#define BP_CLPCR_STBY_COUNT 9
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#define BM_CLPCR_STBY_COUNT (0x3 << 9)
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#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
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#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
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#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
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#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
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#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
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#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
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#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
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#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
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#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
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#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
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#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
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#define CGPR 0x64
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#define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17)
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#define MX6Q_SUSPEND_OCRAM_SIZE 0x1000
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#define MX6_MAX_MMDC_IO_NUM 33
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static void __iomem *ccm_base;
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static void __iomem *suspend_ocram_base;
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static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
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/*
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* suspend ocram space layout:
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* ======================== high address ======================
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* .
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* .
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* .
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* ^
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* ^
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* ^
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* imx6_suspend code
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* PM_INFO structure(imx6_cpu_pm_info)
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* ======================== low address =======================
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*/
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struct imx6_pm_base {
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phys_addr_t pbase;
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void __iomem *vbase;
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};
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struct imx6_pm_socdata {
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u32 ddr_type;
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const char *mmdc_compat;
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const char *src_compat;
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const char *iomuxc_compat;
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const char *gpc_compat;
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const char *pl310_compat;
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const u32 mmdc_io_num;
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const u32 *mmdc_io_offset;
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};
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static const u32 imx6q_mmdc_io_offset[] __initconst = {
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0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
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0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
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0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
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0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
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0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
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0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
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0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
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0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
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0x74c, /* GPR_ADDS */
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};
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static const u32 imx6dl_mmdc_io_offset[] __initconst = {
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0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
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0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
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0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
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0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
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0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
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0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
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0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
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0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
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0x74c, /* GPR_ADDS */
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};
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static const u32 imx6sl_mmdc_io_offset[] __initconst = {
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0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
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0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
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0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
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0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
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0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */
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};
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static const u32 imx6sx_mmdc_io_offset[] __initconst = {
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0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
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0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
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0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
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0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
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0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
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};
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static const u32 imx6ul_mmdc_io_offset[] __initconst = {
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0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */
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0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */
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0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */
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0x494, 0x4b0, /* MODE_CTL, MODE, */
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};
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static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
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.mmdc_compat = "fsl,imx6q-mmdc",
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.src_compat = "fsl,imx6q-src",
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.iomuxc_compat = "fsl,imx6q-iomuxc",
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.gpc_compat = "fsl,imx6q-gpc",
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.pl310_compat = "arm,pl310-cache",
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.mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
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.mmdc_io_offset = imx6q_mmdc_io_offset,
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};
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static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
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.mmdc_compat = "fsl,imx6q-mmdc",
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.src_compat = "fsl,imx6q-src",
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.iomuxc_compat = "fsl,imx6dl-iomuxc",
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.gpc_compat = "fsl,imx6q-gpc",
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.pl310_compat = "arm,pl310-cache",
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.mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
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.mmdc_io_offset = imx6dl_mmdc_io_offset,
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};
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static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
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.mmdc_compat = "fsl,imx6sl-mmdc",
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.src_compat = "fsl,imx6sl-src",
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.iomuxc_compat = "fsl,imx6sl-iomuxc",
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.gpc_compat = "fsl,imx6sl-gpc",
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.pl310_compat = "arm,pl310-cache",
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.mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
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.mmdc_io_offset = imx6sl_mmdc_io_offset,
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};
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static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
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.mmdc_compat = "fsl,imx6sx-mmdc",
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.src_compat = "fsl,imx6sx-src",
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.iomuxc_compat = "fsl,imx6sx-iomuxc",
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.gpc_compat = "fsl,imx6sx-gpc",
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.pl310_compat = "arm,pl310-cache",
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.mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
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.mmdc_io_offset = imx6sx_mmdc_io_offset,
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};
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static const struct imx6_pm_socdata imx6ul_pm_data __initconst = {
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.mmdc_compat = "fsl,imx6ul-mmdc",
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.src_compat = "fsl,imx6ul-src",
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.iomuxc_compat = "fsl,imx6ul-iomuxc",
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.gpc_compat = "fsl,imx6ul-gpc",
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.pl310_compat = NULL,
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.mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset),
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.mmdc_io_offset = imx6ul_mmdc_io_offset,
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};
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/*
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* This structure is for passing necessary data for low level ocram
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* suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
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* definition is changed, the offset definition in
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* arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
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* otherwise, the suspend to ocram function will be broken!
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*/
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struct imx6_cpu_pm_info {
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phys_addr_t pbase; /* The physical address of pm_info. */
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phys_addr_t resume_addr; /* The physical resume address for asm code */
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u32 ddr_type;
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u32 pm_info_size; /* Size of pm_info. */
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struct imx6_pm_base mmdc_base;
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struct imx6_pm_base src_base;
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struct imx6_pm_base iomuxc_base;
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struct imx6_pm_base ccm_base;
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struct imx6_pm_base gpc_base;
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struct imx6_pm_base l2_base;
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u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
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u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
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} __aligned(8);
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void imx6q_set_int_mem_clk_lpm(bool enable)
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{
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u32 val = readl_relaxed(ccm_base + CGPR);
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val &= ~BM_CGPR_INT_MEM_CLK_LPM;
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if (enable)
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val |= BM_CGPR_INT_MEM_CLK_LPM;
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writel_relaxed(val, ccm_base + CGPR);
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}
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void imx6_enable_rbc(bool enable)
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{
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u32 val;
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/*
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* need to mask all interrupts in GPC before
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* operating RBC configurations
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*/
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imx_gpc_mask_all();
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/* configure RBC enable bit */
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val = readl_relaxed(ccm_base + CCR);
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val &= ~BM_CCR_RBC_EN;
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val |= enable ? BM_CCR_RBC_EN : 0;
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writel_relaxed(val, ccm_base + CCR);
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/* configure RBC count */
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val = readl_relaxed(ccm_base + CCR);
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val &= ~BM_CCR_RBC_BYPASS_COUNT;
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val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
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writel(val, ccm_base + CCR);
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/*
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* need to delay at least 2 cycles of CKIL(32K)
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* due to hardware design requirement, which is
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* ~61us, here we use 65us for safe
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*/
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udelay(65);
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/* restore GPC interrupt mask settings */
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imx_gpc_restore_all();
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}
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static void imx6q_enable_wb(bool enable)
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{
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u32 val;
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/* configure well bias enable bit */
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val = readl_relaxed(ccm_base + CLPCR);
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val &= ~BM_CLPCR_WB_PER_AT_LPM;
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val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
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writel_relaxed(val, ccm_base + CLPCR);
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/* configure well bias count */
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val = readl_relaxed(ccm_base + CCR);
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val &= ~BM_CCR_WB_COUNT;
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val |= enable ? BM_CCR_WB_COUNT : 0;
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writel_relaxed(val, ccm_base + CCR);
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}
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int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
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{
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u32 val = readl_relaxed(ccm_base + CLPCR);
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val &= ~BM_CLPCR_LPM;
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switch (mode) {
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case WAIT_CLOCKED:
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break;
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case WAIT_UNCLOCKED:
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val |= 0x1 << BP_CLPCR_LPM;
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val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
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break;
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case STOP_POWER_ON:
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val |= 0x2 << BP_CLPCR_LPM;
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val &= ~BM_CLPCR_VSTBY;
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val &= ~BM_CLPCR_SBYOS;
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if (cpu_is_imx6sl())
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val |= BM_CLPCR_BYPASS_PMIC_READY;
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if (cpu_is_imx6sl() || cpu_is_imx6sx())
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val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
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else
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val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
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break;
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case WAIT_UNCLOCKED_POWER_OFF:
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val |= 0x1 << BP_CLPCR_LPM;
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val &= ~BM_CLPCR_VSTBY;
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val &= ~BM_CLPCR_SBYOS;
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break;
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case STOP_POWER_OFF:
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val |= 0x2 << BP_CLPCR_LPM;
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val |= 0x3 << BP_CLPCR_STBY_COUNT;
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val |= BM_CLPCR_VSTBY;
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val |= BM_CLPCR_SBYOS;
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if (cpu_is_imx6sl())
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val |= BM_CLPCR_BYPASS_PMIC_READY;
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if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())
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val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
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else
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val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
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break;
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default:
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return -EINVAL;
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}
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/*
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* ERR007265: CCM: When improper low-power sequence is used,
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* the SoC enters low power mode before the ARM core executes WFI.
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*
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* Software workaround:
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* 1) Software should trigger IRQ #32 (IOMUX) to be always pending
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* by setting IOMUX_GPR1_GINT.
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* 2) Software should then unmask IRQ #32 in GPC before setting CCM
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* Low-Power mode.
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* 3) Software should mask IRQ #32 right after CCM Low-Power mode
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* is set (set bits 0-1 of CCM_CLPCR).
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*
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* Note that IRQ #32 is GIC SPI #0.
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*/
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imx_gpc_hwirq_unmask(0);
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writel_relaxed(val, ccm_base + CLPCR);
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imx_gpc_hwirq_mask(0);
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return 0;
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}
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static int imx6q_suspend_finish(unsigned long val)
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{
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if (!imx6_suspend_in_ocram_fn) {
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cpu_do_idle();
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} else {
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/*
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* call low level suspend function in ocram,
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* as we need to float DDR IO.
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*/
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local_flush_tlb_all();
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/* check if need to flush internal L2 cache */
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if (!((struct imx6_cpu_pm_info *)
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suspend_ocram_base)->l2_base.vbase)
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flush_cache_all();
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imx6_suspend_in_ocram_fn(suspend_ocram_base);
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}
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return 0;
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}
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static int imx6q_pm_enter(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_STANDBY:
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imx6_set_lpm(STOP_POWER_ON);
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imx6q_set_int_mem_clk_lpm(true);
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imx_gpc_pre_suspend(false);
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if (cpu_is_imx6sl())
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imx6sl_set_wait_clk(true);
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/* Zzz ... */
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cpu_do_idle();
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if (cpu_is_imx6sl())
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imx6sl_set_wait_clk(false);
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imx_gpc_post_resume();
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imx6_set_lpm(WAIT_CLOCKED);
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break;
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case PM_SUSPEND_MEM:
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imx6_set_lpm(STOP_POWER_OFF);
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imx6q_set_int_mem_clk_lpm(false);
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imx6q_enable_wb(true);
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/*
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* For suspend into ocram, asm code already take care of
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* RBC setting, so we do NOT need to do that here.
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*/
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if (!imx6_suspend_in_ocram_fn)
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imx6_enable_rbc(true);
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imx_gpc_pre_suspend(true);
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imx_anatop_pre_suspend();
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/* Zzz ... */
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cpu_suspend(0, imx6q_suspend_finish);
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if (cpu_is_imx6q() || cpu_is_imx6dl())
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imx_smp_prepare();
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imx_anatop_post_resume();
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imx_gpc_post_resume();
|
|
imx6_enable_rbc(false);
|
|
imx6q_enable_wb(false);
|
|
imx6q_set_int_mem_clk_lpm(true);
|
|
imx6_set_lpm(WAIT_CLOCKED);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int imx6q_pm_valid(suspend_state_t state)
|
|
{
|
|
return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
|
|
}
|
|
|
|
static const struct platform_suspend_ops imx6q_pm_ops = {
|
|
.enter = imx6q_pm_enter,
|
|
.valid = imx6q_pm_valid,
|
|
};
|
|
|
|
static int __init imx6_pm_get_base(struct imx6_pm_base *base,
|
|
const char *compat)
|
|
{
|
|
struct device_node *node;
|
|
struct resource res;
|
|
int ret = 0;
|
|
|
|
node = of_find_compatible_node(NULL, NULL, compat);
|
|
if (!node) {
|
|
ret = -ENODEV;
|
|
goto out;
|
|
}
|
|
|
|
ret = of_address_to_resource(node, 0, &res);
|
|
if (ret)
|
|
goto put_node;
|
|
|
|
base->pbase = res.start;
|
|
base->vbase = ioremap(res.start, resource_size(&res));
|
|
if (!base->vbase)
|
|
ret = -ENOMEM;
|
|
|
|
put_node:
|
|
of_node_put(node);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
|
|
{
|
|
phys_addr_t ocram_pbase;
|
|
struct device_node *node;
|
|
struct platform_device *pdev;
|
|
struct imx6_cpu_pm_info *pm_info;
|
|
struct gen_pool *ocram_pool;
|
|
unsigned long ocram_base;
|
|
int i, ret = 0;
|
|
const u32 *mmdc_offset_array;
|
|
|
|
suspend_set_ops(&imx6q_pm_ops);
|
|
|
|
if (!socdata) {
|
|
pr_warn("%s: invalid argument!\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
node = of_find_compatible_node(NULL, NULL, "mmio-sram");
|
|
if (!node) {
|
|
pr_warn("%s: failed to find ocram node!\n", __func__);
|
|
return -ENODEV;
|
|
}
|
|
|
|
pdev = of_find_device_by_node(node);
|
|
if (!pdev) {
|
|
pr_warn("%s: failed to find ocram device!\n", __func__);
|
|
ret = -ENODEV;
|
|
goto put_node;
|
|
}
|
|
|
|
ocram_pool = gen_pool_get(&pdev->dev, NULL);
|
|
if (!ocram_pool) {
|
|
pr_warn("%s: ocram pool unavailable!\n", __func__);
|
|
ret = -ENODEV;
|
|
goto put_node;
|
|
}
|
|
|
|
ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
|
|
if (!ocram_base) {
|
|
pr_warn("%s: unable to alloc ocram!\n", __func__);
|
|
ret = -ENOMEM;
|
|
goto put_node;
|
|
}
|
|
|
|
ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
|
|
|
|
suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
|
|
MX6Q_SUSPEND_OCRAM_SIZE, false);
|
|
|
|
memset(suspend_ocram_base, 0, sizeof(*pm_info));
|
|
pm_info = suspend_ocram_base;
|
|
pm_info->pbase = ocram_pbase;
|
|
pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
|
|
pm_info->pm_info_size = sizeof(*pm_info);
|
|
|
|
/*
|
|
* ccm physical address is not used by asm code currently,
|
|
* so get ccm virtual address directly.
|
|
*/
|
|
pm_info->ccm_base.vbase = ccm_base;
|
|
|
|
ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
|
|
if (ret) {
|
|
pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
|
|
goto put_node;
|
|
}
|
|
|
|
ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
|
|
if (ret) {
|
|
pr_warn("%s: failed to get src base %d!\n", __func__, ret);
|
|
goto src_map_failed;
|
|
}
|
|
|
|
ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
|
|
if (ret) {
|
|
pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
|
|
goto iomuxc_map_failed;
|
|
}
|
|
|
|
ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
|
|
if (ret) {
|
|
pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
|
|
goto gpc_map_failed;
|
|
}
|
|
|
|
if (socdata->pl310_compat) {
|
|
ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat);
|
|
if (ret) {
|
|
pr_warn("%s: failed to get pl310-cache base %d!\n",
|
|
__func__, ret);
|
|
goto pl310_cache_map_failed;
|
|
}
|
|
}
|
|
|
|
pm_info->ddr_type = imx_mmdc_get_ddr_type();
|
|
pm_info->mmdc_io_num = socdata->mmdc_io_num;
|
|
mmdc_offset_array = socdata->mmdc_io_offset;
|
|
|
|
for (i = 0; i < pm_info->mmdc_io_num; i++) {
|
|
pm_info->mmdc_io_val[i][0] =
|
|
mmdc_offset_array[i];
|
|
pm_info->mmdc_io_val[i][1] =
|
|
readl_relaxed(pm_info->iomuxc_base.vbase +
|
|
mmdc_offset_array[i]);
|
|
}
|
|
|
|
imx6_suspend_in_ocram_fn = fncpy(
|
|
suspend_ocram_base + sizeof(*pm_info),
|
|
&imx6_suspend,
|
|
MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
|
|
|
|
goto put_node;
|
|
|
|
pl310_cache_map_failed:
|
|
iounmap(pm_info->gpc_base.vbase);
|
|
gpc_map_failed:
|
|
iounmap(pm_info->iomuxc_base.vbase);
|
|
iomuxc_map_failed:
|
|
iounmap(pm_info->src_base.vbase);
|
|
src_map_failed:
|
|
iounmap(pm_info->mmdc_base.vbase);
|
|
put_node:
|
|
of_node_put(node);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void __init imx6_pm_common_init(const struct imx6_pm_socdata
|
|
*socdata)
|
|
{
|
|
struct regmap *gpr;
|
|
int ret;
|
|
|
|
WARN_ON(!ccm_base);
|
|
|
|
if (IS_ENABLED(CONFIG_SUSPEND)) {
|
|
ret = imx6q_suspend_init(socdata);
|
|
if (ret)
|
|
pr_warn("%s: No DDR LPM support with suspend %d!\n",
|
|
__func__, ret);
|
|
}
|
|
|
|
/*
|
|
* This is for SW workaround step #1 of ERR007265, see comments
|
|
* in imx6_set_lpm for details of this errata.
|
|
* Force IOMUXC irq pending, so that the interrupt to GPC can be
|
|
* used to deassert dsm_request signal when the signal gets
|
|
* asserted unexpectedly.
|
|
*/
|
|
gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
|
|
if (!IS_ERR(gpr))
|
|
regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
|
|
IMX6Q_GPR1_GINT);
|
|
}
|
|
|
|
void __init imx6_pm_ccm_init(const char *ccm_compat)
|
|
{
|
|
struct device_node *np;
|
|
u32 val;
|
|
|
|
np = of_find_compatible_node(NULL, NULL, ccm_compat);
|
|
ccm_base = of_iomap(np, 0);
|
|
BUG_ON(!ccm_base);
|
|
|
|
/*
|
|
* Initialize CCM_CLPCR_LPM into RUN mode to avoid ARM core
|
|
* clock being shut down unexpectedly by WAIT mode.
|
|
*/
|
|
val = readl_relaxed(ccm_base + CLPCR);
|
|
val &= ~BM_CLPCR_LPM;
|
|
writel_relaxed(val, ccm_base + CLPCR);
|
|
}
|
|
|
|
void __init imx6q_pm_init(void)
|
|
{
|
|
imx6_pm_common_init(&imx6q_pm_data);
|
|
}
|
|
|
|
void __init imx6dl_pm_init(void)
|
|
{
|
|
imx6_pm_common_init(&imx6dl_pm_data);
|
|
}
|
|
|
|
void __init imx6sl_pm_init(void)
|
|
{
|
|
imx6_pm_common_init(&imx6sl_pm_data);
|
|
}
|
|
|
|
void __init imx6sx_pm_init(void)
|
|
{
|
|
imx6_pm_common_init(&imx6sx_pm_data);
|
|
}
|
|
|
|
void __init imx6ul_pm_init(void)
|
|
{
|
|
imx6_pm_common_init(&imx6ul_pm_data);
|
|
}
|