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Improved and new platform support for various SoCs: - New SoC support: - Broadcom BCM23550 - Freescale i.MX7Solo - Qualcomm MDM9615 - Renesas r8a7792 - Conversion of clps711x to multiplatform - debug uart improvements for Atmel platforms - Tango platform improvements: HOTPLUG_CPU, Suspend-to-ram - OMAP tweaks and improvements to hwmod - OMAP support for kexec on SMP -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXnaibAAoJEIwa5zzehBx3h6AP/0TBATiDuYXTcX3V8zZ/ia9y 7dWbP7gVX7DN39b5qdjLTa+DUx3Y3msxW9qsuUQR8RWijbqjCH7b/fyPwGA0fmpP 3uZpFpyzs+6/3TiMDN1yw1T+/2YbVyM+4rOeNsCwncdXjGSx0FaMJAqLBrppiWLH 1S9HhD/314znibl8skOy8QIDWwlW011sS2mNUIN+JelvnS/VDjtCDfpphpNrAQF9 MZB6LhT9itvf6mIEGIsaDq/Ii7fgIAnA9WCtwv9tJkAZHzbS0cWkiJzb7hF1GzFO Q5HBAyzn+CkeTQ3+9NQU0G0vhfa3Ea0g1gfw6qRmAw+z8Qdiamjh8SSve6zm1fE8 GmIewsMAWWIUYykEIi9hbWCTYq06Pw/Nn6KWRAuQ/lpt++jzMQ82qk6cxELLW15e uAC1JjFOCIFNBZhkrdQDU0qx6Ew/AUH4wCYqu4Xh7pW0MHu0V9NgsmooeoTmCkpd WtgKp8Wh5dsK3SdsbTjdR/IeHSQkeSdgNY/6TBTjpRwCIlEMwHlKbvwvRExk1xzi nLQJsR49MsjeSdPflzO6WUzOjJhQfuw2jCtAQjlom15EgkEZ569MT4RsAQIgvNCI PeUWkvIW1uCtW7Y6ADPRBKMIrajPs8YW4E/xTItuhrqLHp8z6efvRmVNdpzqBTVj tT2t2bRXF0cGiUvOeU7U =Kh9P -----END PGP SIGNATURE----- Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Olof Johansson: "Improved and new platform support for various SoCs: New SoC support: - Broadcom BCM23550 - Freescale i.MX7Solo - Qualcomm MDM9615 - Renesas r8a7792 Improvements: - convert clps711x to multiplatform - debug uart improvements for Atmel platforms - Tango platform improvements: HOTPLUG_CPU, Suspend-to-ram - OMAP tweaks and improvements to hwmod - OMAP support for kexec on SMP" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (109 commits) ARM: davinci: fix build break because of undeclared dm365_evm_snd_data ARM: s3c64xx: smartq: Avoid sparse warnings ARM: sti: Implement dummy L2 cache's write_sec ARM: STi: Update machine _namestr to be more generic. arm: meson: explicitly select clk drivers ARM: tango: add Suspend-to-RAM support ARM: hisi: consolidate the hisilicon machine entries ARM: tango: fix CONFIG_HOTPLUG_CPU=n build MAINTAINERS: Update BCM281XX/BCM11XXX/BCM216XX entry MAINTAINERS: Update BCM63XX entry MAINTAINERS: Add NS2 entry MAINTAINERS: Fix nsp false-positives MAINTAINERS: Change L to M for Broadcom ARM/ARM64 SoC entries ARM: debug: Enable DEBUG_BCM_5301X for Northstar Plus SoCs ARM: clps711x: Switch to MULTIPLATFORM ARM: clps711x: Remove boards support ARM: clps711x: Add basic DT support ARM: clps711x: Reduce static map size ARM: SAMSUNG: Constify iomem address passed to s5p_init_cpu ARM: oxnas: Change OX810SE default driver config ...
156 lines
4.3 KiB
C
156 lines
4.3 KiB
C
/*
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* Amstrad E3 FIQ handling
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*
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* Copyright (C) 2009 Janusz Krzysztofik
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* Copyright (c) 2006 Matt Callow
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* Copyright (c) 2004 Amstrad Plc
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* Copyright (C) 2001 RidgeRun, Inc.
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*
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* Parts of this code are taken from linux/arch/arm/mach-omap/irq.c
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* in the MontaVista 2.4 kernel (and the Amstrad changes therein)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <mach/board-ams-delta.h>
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#include <asm/fiq.h>
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#include <mach/ams-delta-fiq.h>
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static struct fiq_handler fh = {
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.name = "ams-delta-fiq"
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};
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/*
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* This buffer is shared between FIQ and IRQ contexts.
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* The FIQ and IRQ isrs can both read and write it.
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* It is structured as a header section several 32bit slots,
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* followed by the circular buffer where the FIQ isr stores
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* keystrokes received from the qwerty keyboard.
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* See ams-delta-fiq.h for details of offsets.
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*/
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unsigned int fiq_buffer[1024];
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EXPORT_SYMBOL(fiq_buffer);
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static unsigned int irq_counter[16];
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static irqreturn_t deferred_fiq(int irq, void *dev_id)
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{
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int gpio, irq_num, fiq_count;
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struct irq_chip *irq_chip;
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irq_chip = irq_get_chip(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK));
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/*
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* For each handled GPIO interrupt, keep calling its interrupt handler
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* until the IRQ counter catches the FIQ incremented interrupt counter.
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*/
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for (gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK;
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gpio <= AMS_DELTA_GPIO_PIN_HOOK_SWITCH; gpio++) {
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irq_num = gpio_to_irq(gpio);
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fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio];
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while (irq_counter[gpio] < fiq_count) {
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if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
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struct irq_data *d = irq_get_irq_data(irq_num);
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/*
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* It looks like handle_edge_irq() that
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* OMAP GPIO edge interrupts default to,
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* expects interrupt already unmasked.
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*/
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if (irq_chip && irq_chip->irq_unmask)
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irq_chip->irq_unmask(d);
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}
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generic_handle_irq(irq_num);
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irq_counter[gpio]++;
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}
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}
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return IRQ_HANDLED;
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}
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void __init ams_delta_init_fiq(void)
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{
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void *fiqhandler_start;
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unsigned int fiqhandler_length;
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struct pt_regs FIQ_regs;
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unsigned long val, offset;
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int i, retval;
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fiqhandler_start = &qwerty_fiqin_start;
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fiqhandler_length = &qwerty_fiqin_end - &qwerty_fiqin_start;
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pr_info("Installing fiq handler from %p, length 0x%x\n",
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fiqhandler_start, fiqhandler_length);
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retval = claim_fiq(&fh);
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if (retval) {
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pr_err("ams_delta_init_fiq(): couldn't claim FIQ, ret=%d\n",
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retval);
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return;
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}
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retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq,
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IRQ_TYPE_EDGE_RISING, "deferred_fiq", NULL);
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if (retval < 0) {
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pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval);
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release_fiq(&fh);
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return;
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}
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/*
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* Since no set_type() method is provided by OMAP irq chip,
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* switch to edge triggered interrupt type manually.
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*/
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offset = IRQ_ILR0_REG_OFFSET +
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((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4;
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val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1);
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omap_writel(val, DEFERRED_FIQ_IH_BASE + offset);
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set_fiq_handler(fiqhandler_start, fiqhandler_length);
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/*
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* Initialise the buffer which is shared
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* between FIQ mode and IRQ mode
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*/
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fiq_buffer[FIQ_GPIO_INT_MASK] = 0;
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fiq_buffer[FIQ_MASK] = 0;
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fiq_buffer[FIQ_STATE] = 0;
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fiq_buffer[FIQ_KEY] = 0;
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fiq_buffer[FIQ_KEYS_CNT] = 0;
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fiq_buffer[FIQ_KEYS_HICNT] = 0;
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fiq_buffer[FIQ_TAIL_OFFSET] = 0;
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fiq_buffer[FIQ_HEAD_OFFSET] = 0;
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fiq_buffer[FIQ_BUF_LEN] = 256;
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fiq_buffer[FIQ_MISSED_KEYS] = 0;
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fiq_buffer[FIQ_BUFFER_START] =
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(unsigned int) &fiq_buffer[FIQ_CIRC_BUFF];
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for (i = FIQ_CNT_INT_00; i <= FIQ_CNT_INT_15; i++)
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fiq_buffer[i] = 0;
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/*
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* FIQ mode r9 always points to the fiq_buffer, because the FIQ isr
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* will run in an unpredictable context. The fiq_buffer is the FIQ isr's
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* only means of communication with the IRQ level and other kernel
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* context code.
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*/
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FIQ_regs.ARM_r9 = (unsigned int)fiq_buffer;
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set_fiq_regs(&FIQ_regs);
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pr_info("request_fiq(): fiq_buffer = %p\n", fiq_buffer);
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/*
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* Redirect GPIO interrupts to FIQ
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*/
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offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4;
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val = omap_readl(OMAP_IH1_BASE + offset) | 1;
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omap_writel(val, OMAP_IH1_BASE + offset);
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}
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