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![Ivaylo Dimitrov](/assets/img/avatar_default.png)
Commite7b11dc7b7
("ARM: OMAP2+: Fix onenand rate detection to avoid filesystem corruption") partially fixed onenand configuration when GPMC module is reset. Finish the job by also providing the correct values in ONENAND_REG_SYS_CFG1 register. Fixes:e7b11dc7b7
("ARM: OMAP2+: Fix onenand rate detection to avoid filesystem corruption") Cc: stable@vger.kernel.org # v4.2+ Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Tony Lindgren <tony@atomide.com>
407 lines
9.8 KiB
C
407 lines
9.8 KiB
C
/*
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* linux/arch/arm/mach-omap2/gpmc-onenand.c
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*
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* Copyright (C) 2006 - 2009 Nokia Corporation
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* Contacts: Juha Yrjola
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* Tony Lindgren
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/onenand_regs.h>
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#include <linux/io.h>
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#include <linux/omap-gpmc.h>
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#include <linux/platform_data/mtd-onenand-omap2.h>
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#include <linux/err.h>
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#include <asm/mach/flash.h>
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#include "soc.h"
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#define ONENAND_IO_SIZE SZ_128K
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#define ONENAND_FLAG_SYNCREAD (1 << 0)
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#define ONENAND_FLAG_SYNCWRITE (1 << 1)
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#define ONENAND_FLAG_HF (1 << 2)
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#define ONENAND_FLAG_VHF (1 << 3)
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static unsigned onenand_flags;
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static unsigned latency;
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static struct omap_onenand_platform_data *gpmc_onenand_data;
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static struct resource gpmc_onenand_resource = {
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device gpmc_onenand_device = {
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.name = "omap2-onenand",
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.id = -1,
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.num_resources = 1,
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.resource = &gpmc_onenand_resource,
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};
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static struct gpmc_settings onenand_async = {
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.device_width = GPMC_DEVWIDTH_16BIT,
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.mux_add_data = GPMC_MUX_AD,
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};
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static struct gpmc_settings onenand_sync = {
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.burst_read = true,
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.burst_wrap = true,
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.burst_len = GPMC_BURST_16,
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.device_width = GPMC_DEVWIDTH_16BIT,
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.mux_add_data = GPMC_MUX_AD,
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.wait_pin = 0,
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};
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static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
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{
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struct gpmc_device_timings dev_t;
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const int t_cer = 15;
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const int t_avdp = 12;
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const int t_aavdh = 7;
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const int t_ce = 76;
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const int t_aa = 76;
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const int t_oe = 20;
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const int t_cez = 20; /* max of t_cez, t_oez */
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const int t_wpl = 40;
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const int t_wph = 30;
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memset(&dev_t, 0, sizeof(dev_t));
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dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
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dev_t.t_avdp_w = dev_t.t_avdp_r;
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dev_t.t_aavdh = t_aavdh * 1000;
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dev_t.t_aa = t_aa * 1000;
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dev_t.t_ce = t_ce * 1000;
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dev_t.t_oe = t_oe * 1000;
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dev_t.t_cez_r = t_cez * 1000;
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dev_t.t_cez_w = dev_t.t_cez_r;
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dev_t.t_wpl = t_wpl * 1000;
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dev_t.t_wph = t_wph * 1000;
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gpmc_calc_timings(t, &onenand_async, &dev_t);
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}
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static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
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{
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u32 reg;
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/* Ensure sync read and sync write are disabled */
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reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
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reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
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writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
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}
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static void set_onenand_cfg(void __iomem *onenand_base)
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{
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u32 reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT;
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reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
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ONENAND_SYS_CFG1_BL_16;
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if (onenand_flags & ONENAND_FLAG_SYNCREAD)
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reg |= ONENAND_SYS_CFG1_SYNC_READ;
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else
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reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
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if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
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reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
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else
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reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
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if (onenand_flags & ONENAND_FLAG_HF)
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reg |= ONENAND_SYS_CFG1_HF;
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else
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reg &= ~ONENAND_SYS_CFG1_HF;
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if (onenand_flags & ONENAND_FLAG_VHF)
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reg |= ONENAND_SYS_CFG1_VHF;
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else
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reg &= ~ONENAND_SYS_CFG1_VHF;
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writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
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}
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static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
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void __iomem *onenand_base)
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{
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u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
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int freq;
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switch ((ver >> 4) & 0xf) {
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case 0:
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freq = 40;
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break;
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case 1:
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freq = 54;
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break;
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case 2:
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freq = 66;
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break;
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case 3:
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freq = 83;
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break;
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case 4:
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freq = 104;
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break;
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default:
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pr_err("onenand rate not detected, bad GPMC async timings?\n");
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freq = 0;
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}
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return freq;
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}
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static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
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unsigned int flags,
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int freq)
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{
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struct gpmc_device_timings dev_t;
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const int t_cer = 15;
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const int t_avdp = 12;
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const int t_cez = 20; /* max of t_cez, t_oez */
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const int t_wpl = 40;
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const int t_wph = 30;
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int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
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int div, gpmc_clk_ns;
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if (flags & ONENAND_SYNC_READ)
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onenand_flags = ONENAND_FLAG_SYNCREAD;
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else if (flags & ONENAND_SYNC_READWRITE)
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onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
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switch (freq) {
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case 104:
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min_gpmc_clk_period = 9600; /* 104 MHz */
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t_ces = 3;
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t_avds = 4;
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t_avdh = 2;
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t_ach = 3;
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t_aavdh = 6;
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t_rdyo = 6;
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break;
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case 83:
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min_gpmc_clk_period = 12000; /* 83 MHz */
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t_ces = 5;
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t_avds = 4;
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t_avdh = 2;
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t_ach = 6;
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t_aavdh = 6;
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t_rdyo = 9;
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break;
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case 66:
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min_gpmc_clk_period = 15000; /* 66 MHz */
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t_ces = 6;
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t_avds = 5;
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t_avdh = 2;
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t_ach = 6;
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t_aavdh = 6;
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t_rdyo = 11;
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break;
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default:
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min_gpmc_clk_period = 18500; /* 54 MHz */
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t_ces = 7;
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t_avds = 7;
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t_avdh = 7;
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t_ach = 9;
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t_aavdh = 7;
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t_rdyo = 15;
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onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
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break;
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}
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div = gpmc_calc_divider(min_gpmc_clk_period);
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gpmc_clk_ns = gpmc_ticks_to_ns(div);
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if (gpmc_clk_ns < 15) /* >66MHz */
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onenand_flags |= ONENAND_FLAG_HF;
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else
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onenand_flags &= ~ONENAND_FLAG_HF;
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if (gpmc_clk_ns < 12) /* >83MHz */
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onenand_flags |= ONENAND_FLAG_VHF;
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else
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onenand_flags &= ~ONENAND_FLAG_VHF;
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if (onenand_flags & ONENAND_FLAG_VHF)
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latency = 8;
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else if (onenand_flags & ONENAND_FLAG_HF)
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latency = 6;
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else if (gpmc_clk_ns >= 25) /* 40 MHz*/
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latency = 3;
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else
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latency = 4;
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/* Set synchronous read timings */
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memset(&dev_t, 0, sizeof(dev_t));
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if (onenand_flags & ONENAND_FLAG_SYNCREAD)
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onenand_sync.sync_read = true;
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if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
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onenand_sync.sync_write = true;
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onenand_sync.burst_write = true;
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} else {
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dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
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dev_t.t_wpl = t_wpl * 1000;
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dev_t.t_wph = t_wph * 1000;
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dev_t.t_aavdh = t_aavdh * 1000;
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}
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dev_t.ce_xdelay = true;
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dev_t.avd_xdelay = true;
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dev_t.oe_xdelay = true;
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dev_t.we_xdelay = true;
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dev_t.clk = min_gpmc_clk_period;
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dev_t.t_bacc = dev_t.clk;
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dev_t.t_ces = t_ces * 1000;
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dev_t.t_avds = t_avds * 1000;
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dev_t.t_avdh = t_avdh * 1000;
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dev_t.t_ach = t_ach * 1000;
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dev_t.cyc_iaa = (latency + 1);
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dev_t.t_cez_r = t_cez * 1000;
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dev_t.t_cez_w = dev_t.t_cez_r;
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dev_t.cyc_aavdh_oe = 1;
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dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
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gpmc_calc_timings(t, &onenand_sync, &dev_t);
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}
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static int omap2_onenand_setup_async(void __iomem *onenand_base)
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{
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struct gpmc_timings t;
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int ret;
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/*
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* Note that we need to keep sync_write set for the call to
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* omap2_onenand_set_async_mode() to work to detect the onenand
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* supported clock rate for the sync timings.
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*/
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if (gpmc_onenand_data->of_node) {
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gpmc_read_settings_dt(gpmc_onenand_data->of_node,
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&onenand_async);
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if (onenand_async.sync_read || onenand_async.sync_write) {
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if (onenand_async.sync_write)
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gpmc_onenand_data->flags |=
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ONENAND_SYNC_READWRITE;
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else
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gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
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onenand_async.sync_read = false;
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}
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}
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onenand_async.sync_write = true;
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omap2_onenand_calc_async_timings(&t);
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ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
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if (ret < 0)
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return ret;
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ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_async);
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if (ret < 0)
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return ret;
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omap2_onenand_set_async_mode(onenand_base);
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return 0;
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}
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static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
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{
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int ret, freq = *freq_ptr;
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struct gpmc_timings t;
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if (!freq) {
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/* Very first call freq is not known */
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freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
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if (!freq)
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return -ENODEV;
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set_onenand_cfg(onenand_base);
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}
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if (gpmc_onenand_data->of_node) {
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gpmc_read_settings_dt(gpmc_onenand_data->of_node,
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&onenand_sync);
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} else {
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/*
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* FIXME: Appears to be legacy code from initial ONENAND commit.
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* Unclear what boards this is for and if this can be removed.
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*/
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if (!cpu_is_omap34xx())
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onenand_sync.wait_on_read = true;
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}
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omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
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ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
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if (ret < 0)
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return ret;
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ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_sync);
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if (ret < 0)
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return ret;
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set_onenand_cfg(onenand_base);
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*freq_ptr = freq;
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return 0;
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}
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static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
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{
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struct device *dev = &gpmc_onenand_device.dev;
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unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE;
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int ret;
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ret = omap2_onenand_setup_async(onenand_base);
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if (ret) {
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dev_err(dev, "unable to set to async mode\n");
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return ret;
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}
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if (!(gpmc_onenand_data->flags & l))
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return 0;
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ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
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if (ret)
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dev_err(dev, "unable to set to sync mode\n");
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return ret;
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}
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void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
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{
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int err;
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struct device *dev = &gpmc_onenand_device.dev;
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gpmc_onenand_data = _onenand_data;
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gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
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gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
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if (cpu_is_omap24xx() &&
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(gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
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dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
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gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
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gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
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}
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if (cpu_is_omap34xx())
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gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX;
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else
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gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX;
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err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
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(unsigned long *)&gpmc_onenand_resource.start);
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if (err < 0) {
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dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
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gpmc_onenand_data->cs, err);
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return;
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}
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gpmc_onenand_resource.end = gpmc_onenand_resource.start +
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ONENAND_IO_SIZE - 1;
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if (platform_device_register(&gpmc_onenand_device) < 0) {
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dev_err(dev, "Unable to register OneNAND device\n");
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gpmc_cs_free(gpmc_onenand_data->cs);
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return;
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}
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}
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