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![Thomas Gleixner](/assets/img/avatar_default.png)
Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
199 lines
4.6 KiB
C
199 lines
4.6 KiB
C
/*
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* linux/arch/arm/mach-pxa/cm-x2xx-pci.c
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*
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* PCI bios-type initialisation for PCI machines
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*
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* Bits taken from various places.
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*
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* Copyright (C) 2007, 2008 Compulab, Ltd.
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* Mike Rapoport <mike@compulab.co.il>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <asm/mach/pci.h>
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#include <asm/mach-types.h>
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#include <asm/hardware/it8152.h>
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void __iomem *it8152_base_address;
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static int cmx2xx_it8152_irq_gpio;
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static void cmx2xx_it8152_irq_demux(struct irq_desc *desc)
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{
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/* clear our parent irq */
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desc->irq_data.chip->irq_ack(&desc->irq_data);
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it8152_irq_demux(desc);
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}
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void __cmx2xx_pci_init_irq(int irq_gpio)
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{
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it8152_init_irq();
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cmx2xx_it8152_irq_gpio = irq_gpio;
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irq_set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING);
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irq_set_chained_handler(gpio_to_irq(irq_gpio),
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cmx2xx_it8152_irq_demux);
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}
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#ifdef CONFIG_PM
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static unsigned long sleep_save_ite[10];
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void __cmx2xx_pci_suspend(void)
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{
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/* save ITE state */
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sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR);
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sleep_save_ite[1] = __raw_readl(IT8152_INTC_LPCNIMR);
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sleep_save_ite[2] = __raw_readl(IT8152_INTC_LPNIAR);
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/* Clear ITE IRQ's */
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__raw_writel((0), IT8152_INTC_PDCNIRR);
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__raw_writel((0), IT8152_INTC_LPCNIRR);
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}
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void __cmx2xx_pci_resume(void)
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{
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/* restore IT8152 state */
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__raw_writel((sleep_save_ite[0]), IT8152_INTC_PDCNIMR);
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__raw_writel((sleep_save_ite[1]), IT8152_INTC_LPCNIMR);
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__raw_writel((sleep_save_ite[2]), IT8152_INTC_LPNIAR);
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}
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#else
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void cmx2xx_pci_suspend(void) {}
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void cmx2xx_pci_resume(void) {}
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#endif
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/* PCI IRQ mapping*/
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static int __init cmx2xx_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq;
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dev_dbg(&dev->dev, "%s: slot=%x, pin=%x\n", __func__, slot, pin);
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irq = it8152_pci_map_irq(dev, slot, pin);
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if (irq)
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return irq;
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/*
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Here comes the ugly part. The routing is baseboard specific,
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but defining a platform for each possible base of CM-X2XX is
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unrealistic. Here we keep mapping for ATXBase and SB-X2XX.
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*/
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/* ATXBASE PCI slot */
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if (slot == 7)
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return IT8152_PCI_INTA;
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/* ATXBase/SB-X2XX CardBus */
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if (slot == 8 || slot == 0)
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return IT8152_PCI_INTB;
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/* ATXBase Ethernet */
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if (slot == 9)
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return IT8152_PCI_INTA;
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/* CM-x255 Onboard Ethernet */
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if (slot == 15)
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return IT8152_PCI_INTC;
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/* SB-x2xx Ethernet */
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if (slot == 16)
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return IT8152_PCI_INTA;
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/* PC104+ interrupt routing */
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if ((slot == 17) || (slot == 19))
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return IT8152_PCI_INTA;
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if ((slot == 18) || (slot == 20))
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return IT8152_PCI_INTB;
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return(0);
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}
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static void cmx2xx_pci_preinit(void)
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{
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pr_info("Initializing CM-X2XX PCI subsystem\n");
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pcibios_min_io = 0;
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pcibios_min_mem = 0;
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__raw_writel(0x800, IT8152_PCI_CFG_ADDR);
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if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) {
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pr_info("PCI Bridge found.\n");
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/* set PCI I/O base at 0 */
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writel(0x848, IT8152_PCI_CFG_ADDR);
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writel(0, IT8152_PCI_CFG_DATA);
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/* set PCI memory base at 0 */
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writel(0x840, IT8152_PCI_CFG_ADDR);
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writel(0, IT8152_PCI_CFG_DATA);
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writel(0x20, IT8152_GPIO_GPDR);
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/* CardBus Controller on ATXbase baseboard */
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writel(0x4000, IT8152_PCI_CFG_ADDR);
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if (readl(IT8152_PCI_CFG_DATA) == 0xAC51104C) {
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pr_info("CardBus Bridge found.\n");
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/* Configure socket 0 */
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writel(0x408C, IT8152_PCI_CFG_ADDR);
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writel(0x1022, IT8152_PCI_CFG_DATA);
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writel(0x4080, IT8152_PCI_CFG_ADDR);
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writel(0x3844d060, IT8152_PCI_CFG_DATA);
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writel(0x4090, IT8152_PCI_CFG_ADDR);
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writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
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0x60440000),
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IT8152_PCI_CFG_DATA);
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writel(0x4018, IT8152_PCI_CFG_ADDR);
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writel(0xb0000000, IT8152_PCI_CFG_DATA);
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/* Configure socket 1 */
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writel(0x418C, IT8152_PCI_CFG_ADDR);
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writel(0x1022, IT8152_PCI_CFG_DATA);
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writel(0x4180, IT8152_PCI_CFG_ADDR);
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writel(0x3844d060, IT8152_PCI_CFG_DATA);
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writel(0x4190, IT8152_PCI_CFG_ADDR);
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writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
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0x60440000),
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IT8152_PCI_CFG_DATA);
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writel(0x4118, IT8152_PCI_CFG_ADDR);
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writel(0xb0000000, IT8152_PCI_CFG_DATA);
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}
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}
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}
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static struct hw_pci cmx2xx_pci __initdata = {
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.map_irq = cmx2xx_pci_map_irq,
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.nr_controllers = 1,
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.ops = &it8152_ops,
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.setup = it8152_pci_setup,
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.preinit = cmx2xx_pci_preinit,
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};
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static int __init cmx2xx_init_pci(void)
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{
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if (machine_is_armcore())
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pci_common_init(&cmx2xx_pci);
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return 0;
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}
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subsys_initcall(cmx2xx_init_pci);
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