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![Robert Jarzmik](/assets/img/avatar_default.png)
"base_irq" needs to be signed for the error handling to work. Also we
can remove the initialization because we re-assign it later.
Fixes: aa8d6b73ea
('ARM: pxa: pxa_cplds: add lubbock and mainstone IO')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
200 lines
4.8 KiB
C
200 lines
4.8 KiB
C
/*
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* Intel Reference Systems cplds
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*
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* Copyright (C) 2014 Robert Jarzmik
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* Cplds motherboard driver, supporting lubbock and mainstone SoC board.
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*/
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#include <linux/bitops.h>
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#include <linux/gpio.h>
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#include <linux/gpio/consumer.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/mfd/core.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#define FPGA_IRQ_MASK_EN 0x0
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#define FPGA_IRQ_SET_CLR 0x10
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#define CPLDS_NB_IRQ 32
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struct cplds {
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void __iomem *base;
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int irq;
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unsigned int irq_mask;
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struct gpio_desc *gpio0;
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struct irq_domain *irqdomain;
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};
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static irqreturn_t cplds_irq_handler(int in_irq, void *d)
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{
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struct cplds *fpga = d;
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unsigned long pending;
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unsigned int bit;
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pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask;
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for_each_set_bit(bit, &pending, CPLDS_NB_IRQ)
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generic_handle_irq(irq_find_mapping(fpga->irqdomain, bit));
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return IRQ_HANDLED;
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}
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static void cplds_irq_mask_ack(struct irq_data *d)
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{
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struct cplds *fpga = irq_data_get_irq_chip_data(d);
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unsigned int cplds_irq = irqd_to_hwirq(d);
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unsigned int set, bit = BIT(cplds_irq);
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fpga->irq_mask &= ~bit;
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writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
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set = readl(fpga->base + FPGA_IRQ_SET_CLR);
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writel(set & ~bit, fpga->base + FPGA_IRQ_SET_CLR);
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}
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static void cplds_irq_unmask(struct irq_data *d)
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{
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struct cplds *fpga = irq_data_get_irq_chip_data(d);
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unsigned int cplds_irq = irqd_to_hwirq(d);
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unsigned int bit = BIT(cplds_irq);
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fpga->irq_mask |= bit;
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writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
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}
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static struct irq_chip cplds_irq_chip = {
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.name = "pxa_cplds",
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.irq_mask_ack = cplds_irq_mask_ack,
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.irq_unmask = cplds_irq_unmask,
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.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
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};
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static int cplds_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct cplds *fpga = d->host_data;
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irq_set_chip_and_handler(irq, &cplds_irq_chip, handle_level_irq);
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irq_set_chip_data(irq, fpga);
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return 0;
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}
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static const struct irq_domain_ops cplds_irq_domain_ops = {
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.xlate = irq_domain_xlate_twocell,
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.map = cplds_irq_domain_map,
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};
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static int cplds_resume(struct platform_device *pdev)
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{
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struct cplds *fpga = platform_get_drvdata(pdev);
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writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
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return 0;
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}
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static int cplds_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct cplds *fpga;
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int ret;
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int base_irq;
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unsigned long irqflags = 0;
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fpga = devm_kzalloc(&pdev->dev, sizeof(*fpga), GFP_KERNEL);
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if (!fpga)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (res) {
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fpga->irq = (unsigned int)res->start;
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irqflags = res->flags;
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}
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if (!fpga->irq)
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return -ENODEV;
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base_irq = platform_get_irq(pdev, 1);
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if (base_irq < 0)
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base_irq = 0;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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fpga->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(fpga->base))
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return PTR_ERR(fpga->base);
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platform_set_drvdata(pdev, fpga);
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writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
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writel(0, fpga->base + FPGA_IRQ_SET_CLR);
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ret = devm_request_irq(&pdev->dev, fpga->irq, cplds_irq_handler,
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irqflags, dev_name(&pdev->dev), fpga);
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if (ret == -ENOSYS)
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return -EPROBE_DEFER;
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if (ret) {
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dev_err(&pdev->dev, "couldn't request main irq%d: %d\n",
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fpga->irq, ret);
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return ret;
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}
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irq_set_irq_wake(fpga->irq, 1);
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fpga->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
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CPLDS_NB_IRQ,
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&cplds_irq_domain_ops, fpga);
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if (!fpga->irqdomain)
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return -ENODEV;
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if (base_irq) {
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ret = irq_create_strict_mappings(fpga->irqdomain, base_irq, 0,
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CPLDS_NB_IRQ);
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if (ret) {
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dev_err(&pdev->dev, "couldn't create the irq mapping %d..%d\n",
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base_irq, base_irq + CPLDS_NB_IRQ);
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return ret;
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}
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}
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return 0;
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}
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static int cplds_remove(struct platform_device *pdev)
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{
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struct cplds *fpga = platform_get_drvdata(pdev);
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irq_set_chip_and_handler(fpga->irq, NULL, NULL);
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return 0;
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}
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static const struct of_device_id cplds_id_table[] = {
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{ .compatible = "intel,lubbock-cplds-irqs", },
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{ .compatible = "intel,mainstone-cplds-irqs", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, cplds_id_table);
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static struct platform_driver cplds_driver = {
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.driver = {
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.name = "pxa_cplds_irqs",
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.of_match_table = of_match_ptr(cplds_id_table),
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},
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.probe = cplds_probe,
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.remove = cplds_remove,
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.resume = cplds_resume,
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};
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module_platform_driver(cplds_driver);
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MODULE_DESCRIPTION("PXA Cplds interrupts driver");
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MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
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MODULE_LICENSE("GPL");
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