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![Mike Leach](/assets/img/avatar_default.png)
The CoreSight specification (ARM IHI 0029E), updates the ID register requirements for components on an AMBA bus, to cover both traditional ARM Primecell type devices, and newer CoreSight and other components. The Peripheral ID (PID) / Component ID (CID) pair is extended in certain cases to uniquely identify components. CoreSight components related to a single function can share Peripheral ID values, and must be further identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI, PMU and Debug hardware of the A35 all share the same PID. Bits 15:12 of the CID are defined to be the device class. Class 0xF remains for PrimeCell and legacy components. Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support at present. Class 0x2-0x8,0xA and 0xD-0xD are presently reserved. The specification futher defines which classes of device use the standard CID/PID pair, and when additional ID registers are required. This patch introduces the amba_cs_uci_id structure which will be used in all coresight drivers for indentification via the private data pointer in the amba_id structure. Existing drivers that currently use the amba_id->data pointer for private data are updated to use the amba_cs_uci_id->data pointer. Macros and inline functions are added to simplify this code. Signed-off-by: Mike Leach <mike.leach@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
498 lines
12 KiB
C
498 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
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*
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* Description: CoreSight Trace Memory Controller driver
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/fs.h>
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#include <linux/miscdevice.h>
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#include <linux/property.h>
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#include <linux/uaccess.h>
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#include <linux/slab.h>
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#include <linux/dma-mapping.h>
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#include <linux/spinlock.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/coresight.h>
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#include <linux/amba/bus.h>
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#include "coresight-priv.h"
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#include "coresight-tmc.h"
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void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
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{
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/* Ensure formatter, unformatter and hardware fifo are empty */
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if (coresight_timeout(drvdata->base,
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TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
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dev_err(drvdata->dev,
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"timeout while waiting for TMC to be Ready\n");
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}
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}
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void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
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{
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u32 ffcr;
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ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
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ffcr |= TMC_FFCR_STOP_ON_FLUSH;
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writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
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ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT);
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writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
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/* Ensure flush completes */
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if (coresight_timeout(drvdata->base,
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TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
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dev_err(drvdata->dev,
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"timeout while waiting for completion of Manual Flush\n");
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}
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tmc_wait_for_tmcready(drvdata);
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}
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void tmc_enable_hw(struct tmc_drvdata *drvdata)
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{
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writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
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}
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void tmc_disable_hw(struct tmc_drvdata *drvdata)
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{
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writel_relaxed(0x0, drvdata->base + TMC_CTL);
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}
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static int tmc_read_prepare(struct tmc_drvdata *drvdata)
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{
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int ret = 0;
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switch (drvdata->config_type) {
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case TMC_CONFIG_TYPE_ETB:
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case TMC_CONFIG_TYPE_ETF:
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ret = tmc_read_prepare_etb(drvdata);
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break;
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case TMC_CONFIG_TYPE_ETR:
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ret = tmc_read_prepare_etr(drvdata);
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break;
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default:
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ret = -EINVAL;
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}
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if (!ret)
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dev_dbg(drvdata->dev, "TMC read start\n");
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return ret;
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}
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static int tmc_read_unprepare(struct tmc_drvdata *drvdata)
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{
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int ret = 0;
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switch (drvdata->config_type) {
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case TMC_CONFIG_TYPE_ETB:
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case TMC_CONFIG_TYPE_ETF:
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ret = tmc_read_unprepare_etb(drvdata);
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break;
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case TMC_CONFIG_TYPE_ETR:
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ret = tmc_read_unprepare_etr(drvdata);
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break;
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default:
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ret = -EINVAL;
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}
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if (!ret)
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dev_dbg(drvdata->dev, "TMC read end\n");
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return ret;
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}
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static int tmc_open(struct inode *inode, struct file *file)
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{
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int ret;
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struct tmc_drvdata *drvdata = container_of(file->private_data,
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struct tmc_drvdata, miscdev);
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ret = tmc_read_prepare(drvdata);
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if (ret)
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return ret;
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nonseekable_open(inode, file);
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dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
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return 0;
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}
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static inline ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata,
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loff_t pos, size_t len, char **bufpp)
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{
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switch (drvdata->config_type) {
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case TMC_CONFIG_TYPE_ETB:
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case TMC_CONFIG_TYPE_ETF:
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return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp);
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case TMC_CONFIG_TYPE_ETR:
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return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp);
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}
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return -EINVAL;
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}
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static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
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loff_t *ppos)
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{
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char *bufp;
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ssize_t actual;
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struct tmc_drvdata *drvdata = container_of(file->private_data,
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struct tmc_drvdata, miscdev);
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actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp);
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if (actual <= 0)
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return 0;
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if (copy_to_user(data, bufp, actual)) {
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dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
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return -EFAULT;
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}
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*ppos += actual;
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dev_dbg(drvdata->dev, "%zu bytes copied\n", actual);
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return actual;
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}
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static int tmc_release(struct inode *inode, struct file *file)
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{
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int ret;
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struct tmc_drvdata *drvdata = container_of(file->private_data,
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struct tmc_drvdata, miscdev);
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ret = tmc_read_unprepare(drvdata);
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if (ret)
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return ret;
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dev_dbg(drvdata->dev, "%s: released\n", __func__);
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return 0;
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}
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static const struct file_operations tmc_fops = {
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.owner = THIS_MODULE,
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.open = tmc_open,
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.read = tmc_read,
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.release = tmc_release,
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.llseek = no_llseek,
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};
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static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid)
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{
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enum tmc_mem_intf_width memwidth;
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/*
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* Excerpt from the TRM:
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*
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* DEVID::MEMWIDTH[10:8]
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* 0x2 Memory interface databus is 32 bits wide.
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* 0x3 Memory interface databus is 64 bits wide.
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* 0x4 Memory interface databus is 128 bits wide.
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* 0x5 Memory interface databus is 256 bits wide.
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*/
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switch (BMVAL(devid, 8, 10)) {
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case 0x2:
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memwidth = TMC_MEM_INTF_WIDTH_32BITS;
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break;
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case 0x3:
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memwidth = TMC_MEM_INTF_WIDTH_64BITS;
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break;
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case 0x4:
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memwidth = TMC_MEM_INTF_WIDTH_128BITS;
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break;
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case 0x5:
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memwidth = TMC_MEM_INTF_WIDTH_256BITS;
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break;
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default:
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memwidth = 0;
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}
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return memwidth;
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}
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#define coresight_tmc_reg(name, offset) \
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coresight_simple_reg32(struct tmc_drvdata, name, offset)
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#define coresight_tmc_reg64(name, lo_off, hi_off) \
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coresight_simple_reg64(struct tmc_drvdata, name, lo_off, hi_off)
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coresight_tmc_reg(rsz, TMC_RSZ);
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coresight_tmc_reg(sts, TMC_STS);
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coresight_tmc_reg(trg, TMC_TRG);
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coresight_tmc_reg(ctl, TMC_CTL);
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coresight_tmc_reg(ffsr, TMC_FFSR);
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coresight_tmc_reg(ffcr, TMC_FFCR);
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coresight_tmc_reg(mode, TMC_MODE);
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coresight_tmc_reg(pscr, TMC_PSCR);
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coresight_tmc_reg(axictl, TMC_AXICTL);
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coresight_tmc_reg(devid, CORESIGHT_DEVID);
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coresight_tmc_reg64(rrp, TMC_RRP, TMC_RRPHI);
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coresight_tmc_reg64(rwp, TMC_RWP, TMC_RWPHI);
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coresight_tmc_reg64(dba, TMC_DBALO, TMC_DBAHI);
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static struct attribute *coresight_tmc_mgmt_attrs[] = {
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&dev_attr_rsz.attr,
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&dev_attr_sts.attr,
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&dev_attr_rrp.attr,
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&dev_attr_rwp.attr,
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&dev_attr_trg.attr,
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&dev_attr_ctl.attr,
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&dev_attr_ffsr.attr,
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&dev_attr_ffcr.attr,
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&dev_attr_mode.attr,
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&dev_attr_pscr.attr,
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&dev_attr_devid.attr,
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&dev_attr_dba.attr,
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&dev_attr_axictl.attr,
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NULL,
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};
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static ssize_t trigger_cntr_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
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unsigned long val = drvdata->trigger_cntr;
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return sprintf(buf, "%#lx\n", val);
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}
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static ssize_t trigger_cntr_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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{
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int ret;
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unsigned long val;
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struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
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ret = kstrtoul(buf, 16, &val);
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if (ret)
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return ret;
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drvdata->trigger_cntr = val;
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return size;
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}
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static DEVICE_ATTR_RW(trigger_cntr);
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static ssize_t buffer_size_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
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return sprintf(buf, "%#x\n", drvdata->size);
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}
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static ssize_t buffer_size_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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{
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int ret;
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unsigned long val;
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struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
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/* Only permitted for TMC-ETRs */
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if (drvdata->config_type != TMC_CONFIG_TYPE_ETR)
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return -EPERM;
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ret = kstrtoul(buf, 0, &val);
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if (ret)
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return ret;
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/* The buffer size should be page aligned */
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if (val & (PAGE_SIZE - 1))
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return -EINVAL;
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drvdata->size = val;
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return size;
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}
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static DEVICE_ATTR_RW(buffer_size);
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static struct attribute *coresight_tmc_attrs[] = {
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&dev_attr_trigger_cntr.attr,
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&dev_attr_buffer_size.attr,
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NULL,
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};
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static const struct attribute_group coresight_tmc_group = {
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.attrs = coresight_tmc_attrs,
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};
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static const struct attribute_group coresight_tmc_mgmt_group = {
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.attrs = coresight_tmc_mgmt_attrs,
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.name = "mgmt",
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};
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const struct attribute_group *coresight_tmc_groups[] = {
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&coresight_tmc_group,
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&coresight_tmc_mgmt_group,
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NULL,
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};
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static inline bool tmc_etr_can_use_sg(struct tmc_drvdata *drvdata)
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{
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return fwnode_property_present(drvdata->dev->fwnode,
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"arm,scatter-gather");
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}
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/* Detect and initialise the capabilities of a TMC ETR */
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static int tmc_etr_setup_caps(struct tmc_drvdata *drvdata,
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u32 devid, void *dev_caps)
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{
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u32 dma_mask = 0;
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/* Set the unadvertised capabilities */
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tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
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if (!(devid & TMC_DEVID_NOSCAT) && tmc_etr_can_use_sg(drvdata))
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tmc_etr_set_cap(drvdata, TMC_ETR_SG);
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/* Check if the AXI address width is available */
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if (devid & TMC_DEVID_AXIAW_VALID)
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dma_mask = ((devid >> TMC_DEVID_AXIAW_SHIFT) &
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TMC_DEVID_AXIAW_MASK);
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/*
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* Unless specified in the device configuration, ETR uses a 40-bit
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* AXI master in place of the embedded SRAM of ETB/ETF.
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*/
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switch (dma_mask) {
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case 32:
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case 40:
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case 44:
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case 48:
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case 52:
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dev_info(drvdata->dev, "Detected dma mask %dbits\n", dma_mask);
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break;
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default:
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dma_mask = 40;
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}
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return dma_set_mask_and_coherent(drvdata->dev, DMA_BIT_MASK(dma_mask));
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}
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static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
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{
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int ret = 0;
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u32 devid;
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void __iomem *base;
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struct device *dev = &adev->dev;
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struct coresight_platform_data *pdata = NULL;
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struct tmc_drvdata *drvdata;
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struct resource *res = &adev->res;
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struct coresight_desc desc = { 0 };
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struct device_node *np = adev->dev.of_node;
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if (np) {
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pdata = of_get_coresight_platform_data(dev, np);
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if (IS_ERR(pdata)) {
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ret = PTR_ERR(pdata);
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goto out;
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}
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adev->dev.platform_data = pdata;
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}
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ret = -ENOMEM;
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drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
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if (!drvdata)
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goto out;
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drvdata->dev = &adev->dev;
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dev_set_drvdata(dev, drvdata);
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/* Validity for the resource is already checked by the AMBA core */
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base)) {
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ret = PTR_ERR(base);
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goto out;
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}
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drvdata->base = base;
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spin_lock_init(&drvdata->spinlock);
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devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
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drvdata->config_type = BMVAL(devid, 6, 7);
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drvdata->memwidth = tmc_get_memwidth(devid);
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if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
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if (np)
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ret = of_property_read_u32(np,
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"arm,buffer-size",
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&drvdata->size);
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if (ret)
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drvdata->size = SZ_1M;
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} else {
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drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
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}
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pm_runtime_put(&adev->dev);
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desc.pdata = pdata;
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desc.dev = dev;
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desc.groups = coresight_tmc_groups;
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switch (drvdata->config_type) {
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case TMC_CONFIG_TYPE_ETB:
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desc.type = CORESIGHT_DEV_TYPE_SINK;
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desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
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desc.ops = &tmc_etb_cs_ops;
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break;
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case TMC_CONFIG_TYPE_ETR:
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desc.type = CORESIGHT_DEV_TYPE_SINK;
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desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
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desc.ops = &tmc_etr_cs_ops;
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ret = tmc_etr_setup_caps(drvdata, devid,
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coresight_get_uci_data(id));
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if (ret)
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goto out;
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break;
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case TMC_CONFIG_TYPE_ETF:
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desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
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desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
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desc.ops = &tmc_etf_cs_ops;
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break;
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default:
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pr_err("%s: Unsupported TMC config\n", pdata->name);
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ret = -EINVAL;
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goto out;
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}
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drvdata->csdev = coresight_register(&desc);
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if (IS_ERR(drvdata->csdev)) {
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ret = PTR_ERR(drvdata->csdev);
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goto out;
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}
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drvdata->miscdev.name = pdata->name;
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drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
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drvdata->miscdev.fops = &tmc_fops;
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ret = misc_register(&drvdata->miscdev);
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if (ret)
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coresight_unregister(drvdata->csdev);
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out:
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return ret;
|
|
}
|
|
|
|
static const struct amba_id tmc_ids[] = {
|
|
CS_AMBA_ID(0x000bb961),
|
|
/* Coresight SoC 600 TMC-ETR/ETS */
|
|
CS_AMBA_ID_DATA(0x000bb9e8, (unsigned long)CORESIGHT_SOC_600_ETR_CAPS),
|
|
/* Coresight SoC 600 TMC-ETB */
|
|
CS_AMBA_ID(0x000bb9e9),
|
|
/* Coresight SoC 600 TMC-ETF */
|
|
CS_AMBA_ID(0x000bb9ea),
|
|
{ 0, 0},
|
|
};
|
|
|
|
static struct amba_driver tmc_driver = {
|
|
.drv = {
|
|
.name = "coresight-tmc",
|
|
.owner = THIS_MODULE,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.probe = tmc_probe,
|
|
.id_table = tmc_ids,
|
|
};
|
|
builtin_amba_driver(tmc_driver);
|