mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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f83ccb9358
A large part of the arm-soc patches are nowadays DT changes, adding support for new SoCs, boards and devices without changing kernel source. The plan is still to move the devicetree files out of the kernel tree and reduce the amount of churn going on here, but we keep finding reasons to delay doing that. Changes are really all over the place, with little sticking out particularly. We have contributions from a total of 116 people in this branch. Unfortunately, the size of this branch also causes a significant number of conflicts at the moment, typically when subsystem maintainers merge patches that change the driver at the same time as the dts files. In most cases this could be avoided because the dts changes are supposed to be compatible in both ways, and we are asking everyone to send ARM dts changes through our tree only. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUz/11WCrR//JCVInAQIIyRAA0DjdNNQ/A4G2i1nZCiTFH6a4oZy4JarN ATVPkW/V8avhh+yVNe5FWA44Xe6CDC5TXwMaIsbK+w3Iclj3fplh/MsBkQ9ZT9Sl LAjJoOjuYucCeDy0WLVioRKZ4PJEDoCu/oZTauIMnmWCOCRxLYpOM3FkAT9oN/Ti lswpTSLiV1/U3ZSI4M3qn+Sx1VJL8c/hAIWbvf5if2diYkWPk3VOSKyxmD9zLWdD Iqtb79J+ETVeOIM4sHnx79cG4ZCdpOfRAl7qx6hkJu0YATXESxWhpXVE2McTJuzM qHKsRRNSfsfSWPeF4angll9o06X/qgdT6C4P2dfH49lGeG7llOttw3OaCx3hWCTe U5bt26qtbwG2ZbzocaqvideP+rbpQrCH2vdO1embPv5Lu6peMoBWjxy6twSVXJBG LIymJ0IbiGYxL7BReGqRXt6ehy0BDWBeTSTdsGqgEl2TnxHuS/kgGfJc4D5riiEk aRPVq10p/k+yo4BZtq2GqXIOG6cqkIQ5lhl5Tg9+MfUlquAONqJP70FgRJDBIw9L 9uJp71bgSsA6eYg2tXoqJtpdjKplDWavgtACzIkFg2qFLyYmKvx+F0AXbeTIsrri /mIchTyG+dgiIjWvj/Xsf7jhrdzRcl3uKsJwFmk927pIsh24HV8T+LKgHrf+sVcO qEsEnKGYA6s= =zl/N -----END PGP SIGNATURE----- Merge tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device tree changes from Arnd Bergmann: "A large part of the arm-soc patches are nowadays DT changes, adding support for new SoCs, boards and devices without changing kernel source. The plan is still to move the devicetree files out of the kernel tree and reduce the amount of churn going on here, but we keep finding reasons to delay doing that. Changes are really all over the place, with little sticking out particularly. We have contributions from a total of 116 people in this branch. Unfortunately, the size of this branch also causes a significant number of conflicts at the moment, typically when subsystem maintainers merge patches that change the driver at the same time as the dts files. In most cases this could be avoided because the dts changes are supposed to be compatible in both ways, and we are asking everyone to send ARM dts changes through our tree only" * tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (541 commits) dts: stmmac: Document the clocks property in the stmmac base document dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac. ARM: STi: stih41x: Add support for the FSM Serial Flash Controller ARM: STi: stih416: Add support for the FSM Serial Flash Controller ARM: tegra: fix Dalmore pinctrl configuration ARM: dts: keystone: use common "ti,keystone" compatible instead of -evm ARM: dts: k2hk-evm: set ubifs partition size for 512M NAND ARM: dts: Build all keystone dt blobs ARM: dts: keystone: Fix control register range for clktsip ARM: dts: keystone: Fix domain register range for clkfftc1 ARM: dts: bcm28155-ap: leave camldo1 on to fix reboot ARM: dts: add bcm590xx pmu support and enable for bcm28155-ap ARM: dts: bcm21664: Add device tree files. ARM: DT: bcm21664: Device tree bindings ARM: efm32: properly namespace i2c location property ARM: efm32: fix unit address part in USART2 device nodes' names ARM: mvebu: Enable NAND controller in Armada 385-DB ARM: mvebu: Add support for NAND controller in Armada 38x SoC ARM: mvebu: Add the Core Divider clock to Armada 38x SoCs ARM: mvebu: Add a 2 GHz fixed-clock on Armada 38x SoCs ...
492 lines
11 KiB
Text
492 lines
11 KiB
Text
/*
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* Copyright 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "skeleton.dtsi"
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/ {
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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cpu@2 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <3>;
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};
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};
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memory {
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reg = <0x40000000 0x80000000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: osc24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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osc32k: clk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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pll1: clk@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun6i-a31-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll1";
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};
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pll6: clk@01c20028 {
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#clock-cells = <0>;
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compatible = "allwinner,sun6i-a31-pll6-clk";
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6";
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};
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cpu: cpu@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-cpu-clk";
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reg = <0x01c20050 0x4>;
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/*
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* PLL1 is listed twice here.
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* While it looks suspicious, it's actually documented
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* that way both in the datasheet and in the code from
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* Allwinner.
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*/
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
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clock-output-names = "cpu";
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};
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axi: axi@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-axi-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&cpu>;
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clock-output-names = "axi";
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};
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ahb1_mux: ahb1_mux@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
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clock-output-names = "ahb1_mux";
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};
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ahb1: ahb1@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-ahb-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb1_mux>;
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clock-output-names = "ahb1";
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};
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ahb1_gates: clk@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
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reg = <0x01c20060 0x8>;
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clocks = <&ahb1>;
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clock-output-names = "ahb1_mipidsi", "ahb1_ss",
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"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
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"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
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"ahb1_nand0", "ahb1_sdram",
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"ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
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"ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
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"ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
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"ahb1_ehci1", "ahb1_ohci0",
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"ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
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"ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
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"ahb1_hdmi", "ahb1_de0", "ahb1_de1",
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"ahb1_fe0", "ahb1_fe1", "ahb1_mp",
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"ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
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"ahb1_drc0", "ahb1_drc1";
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};
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apb1: apb1@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb0-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb1>;
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clock-output-names = "apb1";
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};
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apb1_gates: clk@01c20068 {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-apb1-gates-clk";
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reg = <0x01c20068 0x4>;
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clocks = <&apb1>;
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clock-output-names = "apb1_codec", "apb1_digital_mic",
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"apb1_pio", "apb1_daudio0",
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"apb1_daudio1";
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};
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apb2_mux: apb2_mux@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb1-mux-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
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clock-output-names = "apb2_mux";
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};
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apb2: apb2@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun6i-a31-apb2-div-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&apb2_mux>;
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clock-output-names = "apb2";
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};
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apb2_gates: clk@01c2006c {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-apb2-gates-clk";
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reg = <0x01c2006c 0x4>;
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clocks = <&apb2>;
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clock-output-names = "apb2_i2c0", "apb2_i2c1",
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"apb2_i2c2", "apb2_i2c3", "apb2_uart0",
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"apb2_uart1", "apb2_uart2", "apb2_uart3",
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"apb2_uart4", "apb2_uart5";
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};
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spi0_clk: clk@01c200a0 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200a0 0x4>;
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clocks = <&osc24M>, <&pll6>;
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clock-output-names = "spi0";
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};
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spi1_clk: clk@01c200a4 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200a4 0x4>;
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clocks = <&osc24M>, <&pll6>;
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clock-output-names = "spi1";
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};
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spi2_clk: clk@01c200a8 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200a8 0x4>;
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clocks = <&osc24M>, <&pll6>;
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clock-output-names = "spi2";
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};
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spi3_clk: clk@01c200ac {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200ac 0x4>;
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clocks = <&osc24M>, <&pll6>;
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clock-output-names = "spi3";
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};
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};
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soc@01c00000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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nmi_intc: interrupt-controller@01f00c0c {
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compatible = "allwinner,sun6i-a31-sc-nmi";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x01f00c0c 0x38>;
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interrupts = <0 32 4>;
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};
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pio: pinctrl@01c20800 {
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compatible = "allwinner,sun6i-a31-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <0 11 4>,
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<0 15 4>,
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<0 16 4>,
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<0 17 4>;
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clocks = <&apb1_gates 5>;
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gpio-controller;
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interrupt-controller;
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#address-cells = <1>;
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#size-cells = <0>;
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#gpio-cells = <3>;
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uart0_pins_a: uart0@0 {
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allwinner,pins = "PH20", "PH21";
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allwinner,function = "uart0";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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i2c0_pins_a: i2c0@0 {
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allwinner,pins = "PH14", "PH15";
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allwinner,function = "i2c0";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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i2c1_pins_a: i2c1@0 {
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allwinner,pins = "PH16", "PH17";
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allwinner,function = "i2c1";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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i2c2_pins_a: i2c2@0 {
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allwinner,pins = "PH18", "PH19";
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allwinner,function = "i2c2";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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};
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ahb1_rst: reset@01c202c0 {
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#reset-cells = <1>;
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compatible = "allwinner,sun6i-a31-ahb1-reset";
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reg = <0x01c202c0 0xc>;
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};
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apb1_rst: reset@01c202d0 {
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#reset-cells = <1>;
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compatible = "allwinner,sun6i-a31-clock-reset";
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reg = <0x01c202d0 0x4>;
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};
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apb2_rst: reset@01c202d8 {
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#reset-cells = <1>;
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compatible = "allwinner,sun6i-a31-clock-reset";
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reg = <0x01c202d8 0x4>;
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};
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timer@01c20c00 {
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compatible = "allwinner,sun4i-a10-timer";
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reg = <0x01c20c00 0xa0>;
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interrupts = <0 18 4>,
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<0 19 4>,
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<0 20 4>,
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<0 21 4>,
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<0 22 4>;
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clocks = <&osc24M>;
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};
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wdt1: watchdog@01c20ca0 {
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compatible = "allwinner,sun6i-a31-wdt";
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reg = <0x01c20ca0 0x20>;
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};
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uart0: serial@01c28000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28000 0x400>;
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interrupts = <0 0 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb2_gates 16>;
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resets = <&apb2_rst 16>;
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status = "disabled";
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};
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uart1: serial@01c28400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28400 0x400>;
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interrupts = <0 1 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb2_gates 17>;
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resets = <&apb2_rst 17>;
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status = "disabled";
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};
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uart2: serial@01c28800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28800 0x400>;
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interrupts = <0 2 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb2_gates 18>;
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resets = <&apb2_rst 18>;
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status = "disabled";
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};
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uart3: serial@01c28c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28c00 0x400>;
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interrupts = <0 3 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb2_gates 19>;
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resets = <&apb2_rst 19>;
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status = "disabled";
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};
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uart4: serial@01c29000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29000 0x400>;
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interrupts = <0 4 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb2_gates 20>;
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resets = <&apb2_rst 20>;
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status = "disabled";
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};
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uart5: serial@01c29400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29400 0x400>;
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interrupts = <0 5 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb2_gates 21>;
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resets = <&apb2_rst 21>;
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status = "disabled";
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};
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i2c0: i2c@01c2ac00 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2ac00 0x400>;
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interrupts = <0 6 4>;
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clocks = <&apb2_gates 0>;
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clock-frequency = <100000>;
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resets = <&apb2_rst 0>;
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status = "disabled";
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};
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i2c1: i2c@01c2b000 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2b000 0x400>;
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interrupts = <0 7 4>;
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clocks = <&apb2_gates 1>;
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clock-frequency = <100000>;
|
|
resets = <&apb2_rst 1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@01c2b400 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b400 0x400>;
|
|
interrupts = <0 8 4>;
|
|
clocks = <&apb2_gates 2>;
|
|
clock-frequency = <100000>;
|
|
resets = <&apb2_rst 2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@01c2b800 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b800 0x400>;
|
|
interrupts = <0 9 4>;
|
|
clocks = <&apb2_gates 3>;
|
|
clock-frequency = <100000>;
|
|
resets = <&apb2_rst 3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@01c68000 {
|
|
compatible = "allwinner,sun6i-a31-spi";
|
|
reg = <0x01c68000 0x1000>;
|
|
interrupts = <0 65 4>;
|
|
clocks = <&ahb1_gates 20>, <&spi0_clk>;
|
|
clock-names = "ahb", "mod";
|
|
resets = <&ahb1_rst 20>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@01c69000 {
|
|
compatible = "allwinner,sun6i-a31-spi";
|
|
reg = <0x01c69000 0x1000>;
|
|
interrupts = <0 66 4>;
|
|
clocks = <&ahb1_gates 21>, <&spi1_clk>;
|
|
clock-names = "ahb", "mod";
|
|
resets = <&ahb1_rst 21>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@01c6a000 {
|
|
compatible = "allwinner,sun6i-a31-spi";
|
|
reg = <0x01c6a000 0x1000>;
|
|
interrupts = <0 67 4>;
|
|
clocks = <&ahb1_gates 22>, <&spi2_clk>;
|
|
clock-names = "ahb", "mod";
|
|
resets = <&ahb1_rst 22>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@01c6b000 {
|
|
compatible = "allwinner,sun6i-a31-spi";
|
|
reg = <0x01c6b000 0x1000>;
|
|
interrupts = <0 68 4>;
|
|
clocks = <&ahb1_gates 23>, <&spi3_clk>;
|
|
clock-names = "ahb", "mod";
|
|
resets = <&ahb1_rst 23>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@01c81000 {
|
|
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
|
|
reg = <0x01c81000 0x1000>,
|
|
<0x01c82000 0x1000>,
|
|
<0x01c84000 0x2000>,
|
|
<0x01c86000 0x2000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <1 9 0xf04>;
|
|
};
|
|
|
|
cpucfg@01f01c00 {
|
|
compatible = "allwinner,sun6i-a31-cpuconfig";
|
|
reg = <0x01f01c00 0x300>;
|
|
};
|
|
|
|
prcm@01f01c00 {
|
|
compatible = "allwinner,sun6i-a31-prcm";
|
|
reg = <0x01f01400 0x200>;
|
|
};
|
|
};
|
|
};
|