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85e7652d89
Commit 1ee46ebd("ASoC: Make the DAI ops constant in the DAI structure") introduced the possibility to have constant DAI ops structures, yet this is barley used in both existing drivers and also new drivers being submitted, although none of them modifies its DAI ops structure. The later is not surprising since existing drivers are often used as templates for new drivers. So this patch just constifies all existing snd_soc_dai_ops structs to eliminate the issue altogether. The patch was generated with the following coccinelle semantic patch: // <smpl> @@ identifier ops; @@ -struct snd_soc_dai_ops ops = +const struct snd_soc_dai_ops ops = { ... }; // </smpl> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
642 lines
16 KiB
C
642 lines
16 KiB
C
/*
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* uda134x.c -- UDA134X ALSA SoC Codec driver
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*
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* Modifications by Christian Pellegrin <chripell@evolware.org>
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*
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* Copyright 2007 Dension Audio Systems Ltd.
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* Author: Zoltan Devai
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*
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* Based on the WM87xx drivers by Liam Girdwood and Richard Purdie
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/initval.h>
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#include <sound/uda134x.h>
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#include <sound/l3.h>
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#include "uda134x.h"
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#define UDA134X_RATES SNDRV_PCM_RATE_8000_48000
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#define UDA134X_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE)
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struct uda134x_priv {
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int sysclk;
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int dai_fmt;
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struct snd_pcm_substream *master_substream;
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struct snd_pcm_substream *slave_substream;
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};
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/* In-data addresses are hard-coded into the reg-cache values */
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static const char uda134x_reg[UDA134X_REGS_NUM] = {
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/* Extended address registers */
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0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* Status, data regs */
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0x00, 0x83, 0x00, 0x40, 0x80, 0xC0, 0x00,
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};
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/*
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* The codec has no support for reading its registers except for peak level...
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*/
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static inline unsigned int uda134x_read_reg_cache(struct snd_soc_codec *codec,
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unsigned int reg)
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{
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u8 *cache = codec->reg_cache;
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if (reg >= UDA134X_REGS_NUM)
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return -1;
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return cache[reg];
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}
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/*
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* Write the register cache
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*/
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static inline void uda134x_write_reg_cache(struct snd_soc_codec *codec,
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u8 reg, unsigned int value)
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{
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u8 *cache = codec->reg_cache;
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if (reg >= UDA134X_REGS_NUM)
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return;
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cache[reg] = value;
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}
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/*
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* Write to the uda134x registers
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*
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*/
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static int uda134x_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value)
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{
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int ret;
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u8 addr;
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u8 data = value;
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struct uda134x_platform_data *pd = codec->control_data;
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pr_debug("%s reg: %02X, value:%02X\n", __func__, reg, value);
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if (reg >= UDA134X_REGS_NUM) {
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printk(KERN_ERR "%s unknown register: reg: %u",
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__func__, reg);
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return -EINVAL;
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}
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uda134x_write_reg_cache(codec, reg, value);
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switch (reg) {
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case UDA134X_STATUS0:
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case UDA134X_STATUS1:
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addr = UDA134X_STATUS_ADDR;
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break;
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case UDA134X_DATA000:
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case UDA134X_DATA001:
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case UDA134X_DATA010:
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case UDA134X_DATA011:
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addr = UDA134X_DATA0_ADDR;
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break;
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case UDA134X_DATA1:
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addr = UDA134X_DATA1_ADDR;
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break;
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default:
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/* It's an extended address register */
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addr = (reg | UDA134X_EXTADDR_PREFIX);
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ret = l3_write(&pd->l3,
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UDA134X_DATA0_ADDR, &addr, 1);
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if (ret != 1)
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return -EIO;
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addr = UDA134X_DATA0_ADDR;
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data = (value | UDA134X_EXTDATA_PREFIX);
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break;
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}
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ret = l3_write(&pd->l3,
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addr, &data, 1);
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if (ret != 1)
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return -EIO;
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return 0;
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}
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static inline void uda134x_reset(struct snd_soc_codec *codec)
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{
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u8 reset_reg = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
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uda134x_write(codec, UDA134X_STATUS0, reset_reg | (1<<6));
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msleep(1);
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uda134x_write(codec, UDA134X_STATUS0, reset_reg & ~(1<<6));
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}
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static int uda134x_mute(struct snd_soc_dai *dai, int mute)
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{
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struct snd_soc_codec *codec = dai->codec;
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u8 mute_reg = uda134x_read_reg_cache(codec, UDA134X_DATA010);
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pr_debug("%s mute: %d\n", __func__, mute);
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if (mute)
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mute_reg |= (1<<2);
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else
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mute_reg &= ~(1<<2);
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uda134x_write(codec, UDA134X_DATA010, mute_reg);
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return 0;
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}
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static int uda134x_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_codec *codec =rtd->codec;
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struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
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struct snd_pcm_runtime *master_runtime;
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if (uda134x->master_substream) {
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master_runtime = uda134x->master_substream->runtime;
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pr_debug("%s constraining to %d bits at %d\n", __func__,
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master_runtime->sample_bits,
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master_runtime->rate);
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snd_pcm_hw_constraint_minmax(substream->runtime,
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SNDRV_PCM_HW_PARAM_RATE,
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master_runtime->rate,
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master_runtime->rate);
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snd_pcm_hw_constraint_minmax(substream->runtime,
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SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
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master_runtime->sample_bits,
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master_runtime->sample_bits);
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uda134x->slave_substream = substream;
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} else
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uda134x->master_substream = substream;
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return 0;
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}
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static void uda134x_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_codec *codec = rtd->codec;
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struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
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if (uda134x->master_substream == substream)
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uda134x->master_substream = uda134x->slave_substream;
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uda134x->slave_substream = NULL;
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}
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static int uda134x_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_codec *codec = rtd->codec;
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struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
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u8 hw_params;
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if (substream == uda134x->slave_substream) {
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pr_debug("%s ignoring hw_params for slave substream\n",
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__func__);
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return 0;
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}
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hw_params = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
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hw_params &= STATUS0_SYSCLK_MASK;
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hw_params &= STATUS0_DAIFMT_MASK;
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pr_debug("%s sysclk: %d, rate:%d\n", __func__,
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uda134x->sysclk, params_rate(params));
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/* set SYSCLK / fs ratio */
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switch (uda134x->sysclk / params_rate(params)) {
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case 512:
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break;
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case 384:
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hw_params |= (1<<4);
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break;
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case 256:
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hw_params |= (1<<5);
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break;
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default:
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printk(KERN_ERR "%s unsupported fs\n", __func__);
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return -EINVAL;
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}
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pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__,
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uda134x->dai_fmt, params_format(params));
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/* set DAI format and word length */
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switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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hw_params |= (1<<1);
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break;
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case SNDRV_PCM_FORMAT_S18_3LE:
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hw_params |= (1<<2);
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break;
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case SNDRV_PCM_FORMAT_S20_3LE:
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hw_params |= ((1<<2) | (1<<1));
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break;
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default:
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printk(KERN_ERR "%s unsupported format (right)\n",
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__func__);
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return -EINVAL;
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}
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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hw_params |= (1<<3);
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break;
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default:
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printk(KERN_ERR "%s unsupported format\n", __func__);
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return -EINVAL;
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}
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uda134x_write(codec, UDA134X_STATUS0, hw_params);
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return 0;
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}
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static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
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int clk_id, unsigned int freq, int dir)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
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pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__,
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clk_id, freq, dir);
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/* Anything between 256fs*8Khz and 512fs*48Khz should be acceptable
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because the codec is slave. Of course limitations of the clock
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master (the IIS controller) apply.
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We'll error out on set_hw_params if it's not OK */
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if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) {
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uda134x->sysclk = freq;
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return 0;
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}
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printk(KERN_ERR "%s unsupported sysclk\n", __func__);
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return -EINVAL;
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}
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static int uda134x_set_dai_fmt(struct snd_soc_dai *codec_dai,
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unsigned int fmt)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
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pr_debug("%s fmt: %08X\n", __func__, fmt);
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/* codec supports only full slave mode */
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if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
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printk(KERN_ERR "%s unsupported slave mode\n", __func__);
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return -EINVAL;
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}
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/* no support for clock inversion */
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if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
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printk(KERN_ERR "%s unsupported clock inversion\n", __func__);
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return -EINVAL;
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}
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/* We can't setup DAI format here as it depends on the word bit num */
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/* so let's just store the value for later */
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uda134x->dai_fmt = fmt;
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return 0;
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}
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static int uda134x_set_bias_level(struct snd_soc_codec *codec,
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enum snd_soc_bias_level level)
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{
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u8 reg;
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struct uda134x_platform_data *pd = codec->control_data;
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int i;
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u8 *cache = codec->reg_cache;
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pr_debug("%s bias level %d\n", __func__, level);
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switch (level) {
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case SND_SOC_BIAS_ON:
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/* ADC, DAC on */
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switch (pd->model) {
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case UDA134X_UDA1340:
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case UDA134X_UDA1344:
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case UDA134X_UDA1345:
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reg = uda134x_read_reg_cache(codec, UDA134X_DATA011);
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uda134x_write(codec, UDA134X_DATA011, reg | 0x03);
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break;
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case UDA134X_UDA1341:
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reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
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uda134x_write(codec, UDA134X_STATUS1, reg | 0x03);
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break;
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default:
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printk(KERN_ERR "UDA134X SoC codec: "
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"unsupported model %d\n", pd->model);
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return -EINVAL;
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}
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break;
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case SND_SOC_BIAS_PREPARE:
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/* power on */
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if (pd->power) {
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pd->power(1);
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/* Sync reg_cache with the hardware */
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for (i = 0; i < ARRAY_SIZE(uda134x_reg); i++)
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codec->driver->write(codec, i, *cache++);
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}
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break;
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case SND_SOC_BIAS_STANDBY:
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/* ADC, DAC power off */
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switch (pd->model) {
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case UDA134X_UDA1340:
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case UDA134X_UDA1344:
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case UDA134X_UDA1345:
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reg = uda134x_read_reg_cache(codec, UDA134X_DATA011);
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uda134x_write(codec, UDA134X_DATA011, reg & ~(0x03));
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break;
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case UDA134X_UDA1341:
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reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
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uda134x_write(codec, UDA134X_STATUS1, reg & ~(0x03));
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break;
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default:
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printk(KERN_ERR "UDA134X SoC codec: "
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"unsupported model %d\n", pd->model);
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return -EINVAL;
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}
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break;
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case SND_SOC_BIAS_OFF:
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/* power off */
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if (pd->power)
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pd->power(0);
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break;
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}
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codec->dapm.bias_level = level;
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return 0;
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}
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static const char *uda134x_dsp_setting[] = {"Flat", "Minimum1",
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"Minimum2", "Maximum"};
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static const char *uda134x_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
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static const char *uda134x_mixmode[] = {"Differential", "Analog1",
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"Analog2", "Both"};
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static const struct soc_enum uda134x_mixer_enum[] = {
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SOC_ENUM_SINGLE(UDA134X_DATA010, 0, 0x04, uda134x_dsp_setting),
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SOC_ENUM_SINGLE(UDA134X_DATA010, 3, 0x04, uda134x_deemph),
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SOC_ENUM_SINGLE(UDA134X_EA010, 0, 0x04, uda134x_mixmode),
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};
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static const struct snd_kcontrol_new uda1341_snd_controls[] = {
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SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
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SOC_SINGLE("Capture Volume", UDA134X_EA010, 2, 0x07, 0),
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SOC_SINGLE("Analog1 Volume", UDA134X_EA000, 0, 0x1F, 1),
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SOC_SINGLE("Analog2 Volume", UDA134X_EA001, 0, 0x1F, 1),
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SOC_SINGLE("Mic Sensitivity", UDA134X_EA010, 2, 7, 0),
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SOC_SINGLE("Mic Volume", UDA134X_EA101, 0, 0x1F, 0),
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SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
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SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
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SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
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SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
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SOC_ENUM("Input Mux", uda134x_mixer_enum[2]),
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SOC_SINGLE("AGC Switch", UDA134X_EA100, 4, 1, 0),
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SOC_SINGLE("AGC Target Volume", UDA134X_EA110, 0, 0x03, 1),
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SOC_SINGLE("AGC Timing", UDA134X_EA110, 2, 0x07, 0),
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SOC_SINGLE("DAC +6dB Switch", UDA134X_STATUS1, 6, 1, 0),
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SOC_SINGLE("ADC +6dB Switch", UDA134X_STATUS1, 5, 1, 0),
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SOC_SINGLE("ADC Polarity Switch", UDA134X_STATUS1, 4, 1, 0),
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SOC_SINGLE("DAC Polarity Switch", UDA134X_STATUS1, 3, 1, 0),
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SOC_SINGLE("Double Speed Playback Switch", UDA134X_STATUS1, 2, 1, 0),
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SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
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};
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static const struct snd_kcontrol_new uda1340_snd_controls[] = {
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SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
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SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
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SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
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SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
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SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
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SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
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};
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static const struct snd_kcontrol_new uda1345_snd_controls[] = {
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SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
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SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
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SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
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};
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static const struct snd_soc_dai_ops uda134x_dai_ops = {
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.startup = uda134x_startup,
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.shutdown = uda134x_shutdown,
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.hw_params = uda134x_hw_params,
|
|
.digital_mute = uda134x_mute,
|
|
.set_sysclk = uda134x_set_dai_sysclk,
|
|
.set_fmt = uda134x_set_dai_fmt,
|
|
};
|
|
|
|
static struct snd_soc_dai_driver uda134x_dai = {
|
|
.name = "uda134x-hifi",
|
|
/* playback capabilities */
|
|
.playback = {
|
|
.stream_name = "Playback",
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = UDA134X_RATES,
|
|
.formats = UDA134X_FORMATS,
|
|
},
|
|
/* capture capabilities */
|
|
.capture = {
|
|
.stream_name = "Capture",
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = UDA134X_RATES,
|
|
.formats = UDA134X_FORMATS,
|
|
},
|
|
/* pcm operations */
|
|
.ops = &uda134x_dai_ops,
|
|
};
|
|
|
|
static int uda134x_soc_probe(struct snd_soc_codec *codec)
|
|
{
|
|
struct uda134x_priv *uda134x;
|
|
struct uda134x_platform_data *pd = codec->card->dev->platform_data;
|
|
|
|
int ret;
|
|
|
|
printk(KERN_INFO "UDA134X SoC Audio Codec\n");
|
|
|
|
if (!pd) {
|
|
printk(KERN_ERR "UDA134X SoC codec: "
|
|
"missing L3 bitbang function\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
switch (pd->model) {
|
|
case UDA134X_UDA1340:
|
|
case UDA134X_UDA1341:
|
|
case UDA134X_UDA1344:
|
|
case UDA134X_UDA1345:
|
|
break;
|
|
default:
|
|
printk(KERN_ERR "UDA134X SoC codec: "
|
|
"unsupported model %d\n",
|
|
pd->model);
|
|
return -EINVAL;
|
|
}
|
|
|
|
uda134x = kzalloc(sizeof(struct uda134x_priv), GFP_KERNEL);
|
|
if (uda134x == NULL)
|
|
return -ENOMEM;
|
|
snd_soc_codec_set_drvdata(codec, uda134x);
|
|
|
|
codec->control_data = pd;
|
|
|
|
if (pd->power)
|
|
pd->power(1);
|
|
|
|
uda134x_reset(codec);
|
|
|
|
if (pd->is_powered_on_standby)
|
|
uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
|
|
else
|
|
uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
|
|
|
|
switch (pd->model) {
|
|
case UDA134X_UDA1340:
|
|
case UDA134X_UDA1344:
|
|
ret = snd_soc_add_controls(codec, uda1340_snd_controls,
|
|
ARRAY_SIZE(uda1340_snd_controls));
|
|
break;
|
|
case UDA134X_UDA1341:
|
|
ret = snd_soc_add_controls(codec, uda1341_snd_controls,
|
|
ARRAY_SIZE(uda1341_snd_controls));
|
|
break;
|
|
case UDA134X_UDA1345:
|
|
ret = snd_soc_add_controls(codec, uda1345_snd_controls,
|
|
ARRAY_SIZE(uda1345_snd_controls));
|
|
break;
|
|
default:
|
|
printk(KERN_ERR "%s unknown codec type: %d",
|
|
__func__, pd->model);
|
|
kfree(uda134x);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "UDA134X: failed to register controls\n");
|
|
kfree(uda134x);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* power down chip */
|
|
static int uda134x_soc_remove(struct snd_soc_codec *codec)
|
|
{
|
|
struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
|
|
|
|
uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
|
|
uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
|
|
|
|
kfree(uda134x);
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_PM)
|
|
static int uda134x_soc_suspend(struct snd_soc_codec *codec,
|
|
pm_message_t state)
|
|
{
|
|
uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
|
|
uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
|
|
return 0;
|
|
}
|
|
|
|
static int uda134x_soc_resume(struct snd_soc_codec *codec)
|
|
{
|
|
uda134x_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
|
|
uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
|
|
return 0;
|
|
}
|
|
#else
|
|
#define uda134x_soc_suspend NULL
|
|
#define uda134x_soc_resume NULL
|
|
#endif /* CONFIG_PM */
|
|
|
|
static struct snd_soc_codec_driver soc_codec_dev_uda134x = {
|
|
.probe = uda134x_soc_probe,
|
|
.remove = uda134x_soc_remove,
|
|
.suspend = uda134x_soc_suspend,
|
|
.resume = uda134x_soc_resume,
|
|
.reg_cache_size = sizeof(uda134x_reg),
|
|
.reg_word_size = sizeof(u8),
|
|
.reg_cache_default = uda134x_reg,
|
|
.reg_cache_step = 1,
|
|
.read = uda134x_read_reg_cache,
|
|
.write = uda134x_write,
|
|
.set_bias_level = uda134x_set_bias_level,
|
|
};
|
|
|
|
static int __devinit uda134x_codec_probe(struct platform_device *pdev)
|
|
{
|
|
return snd_soc_register_codec(&pdev->dev,
|
|
&soc_codec_dev_uda134x, &uda134x_dai, 1);
|
|
}
|
|
|
|
static int __devexit uda134x_codec_remove(struct platform_device *pdev)
|
|
{
|
|
snd_soc_unregister_codec(&pdev->dev);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver uda134x_codec_driver = {
|
|
.driver = {
|
|
.name = "uda134x-codec",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.probe = uda134x_codec_probe,
|
|
.remove = __devexit_p(uda134x_codec_remove),
|
|
};
|
|
|
|
static int __init uda134x_codec_init(void)
|
|
{
|
|
return platform_driver_register(&uda134x_codec_driver);
|
|
}
|
|
module_init(uda134x_codec_init);
|
|
|
|
static void __exit uda134x_codec_exit(void)
|
|
{
|
|
platform_driver_unregister(&uda134x_codec_driver);
|
|
}
|
|
module_exit(uda134x_codec_exit);
|
|
|
|
MODULE_DESCRIPTION("UDA134X ALSA soc codec driver");
|
|
MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
|
|
MODULE_LICENSE("GPL");
|