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65ae8d2621
Hardcode the absence of the MIPS16e2 ASE for all the systems that do so for the MIPS16 ASE already, providing for code to be optimized away. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16097/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
54 lines
1.3 KiB
C
54 lines
1.3 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 Ralf Baechle
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* 6/2004 pf
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*/
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#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
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#include <asm/cpu.h>
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/*
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* IP28 only comes with R10000 family processors all using the same config
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*/
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#define cpu_has_watch 1
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#define cpu_has_mips16 0
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#define cpu_has_mips16e2 0
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#define cpu_has_divec 0
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#define cpu_has_vce 0
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#define cpu_has_cache_cdex_p 0
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#define cpu_has_cache_cdex_s 0
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#define cpu_has_prefetch 1
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#define cpu_has_mcheck 0
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#define cpu_has_ejtag 0
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#define cpu_has_llsc 1
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#define cpu_has_vtag_icache 0
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#define cpu_has_dc_aliases 0 /* see probe_pcache() */
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#define cpu_has_ic_fills_f_dc 0
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#define cpu_has_dsp 0
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#define cpu_has_dsp2 0
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#define cpu_icache_snoops_remote_store 1
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#define cpu_has_mipsmt 0
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#define cpu_has_userlocal 0
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#define cpu_has_nofpuex 0
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#define cpu_has_64bits 1
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#define cpu_has_4kex 1
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#define cpu_has_4k_cache 1
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#define cpu_has_inclusive_pcaches 1
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#define cpu_dcache_line_size() 32
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#define cpu_icache_line_size() 64
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#define cpu_has_mips32r1 0
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#define cpu_has_mips32r2 0
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#define cpu_has_mips64r1 0
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#define cpu_has_mips64r2 0
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#endif /* __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H */
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