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TCR_EL1.TxSZ, which controls the VA space size, is configured by a single kernel image to support either 48-bit or 52-bit VA space. If the ARMv8.2-LVA optional feature is present and we are running with a 64KB page size, then it is possible to use 52-bits of address space for both userspace and kernel addresses. However, any kernel binary that supports 52-bit must also be able to fall back to 48-bit at early boot time if the hardware feature is not present. Since TCR_EL1.T1SZ indicates the size of the memory region addressed by TTBR1_EL1, export the same in vmcoreinfo. User-space utilities like makedumpfile and crash-utility need to read this value from vmcoreinfo for determining if a virtual address lies in the linear map range. While at it also add documentation for TCR_EL1.T1SZ variable being added to vmcoreinfo. It indicates the size offset of the memory region addressed by TTBR1_EL1. Signed-off-by: Bhupesh Sharma <bhsharma@redhat.com> Tested-by: John Donnelly <john.p.donnelly@oracle.com> Tested-by: Kamlakant Patel <kamlakantp@marvell.com> Tested-by: Amit Daniel Kachhap <amit.kachhap@arm.com> Reviewed-by: James Morse <james.morse@arm.com> Reviewed-by: Amit Daniel Kachhap <amit.kachhap@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Steve Capper <steve.capper@arm.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Dave Anderson <anderson@redhat.com> Cc: Kazuhito Hagio <k-hagio@ab.jp.nec.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: kexec@lists.infradead.org Link: https://lore.kernel.org/r/1589395957-24628-3-git-send-email-bhsharma@redhat.com [catalin.marinas@arm.com: removed vabits_actual from the commit log] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
33 lines
952 B
C
33 lines
952 B
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) Linaro.
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* Copyright (C) Huawei Futurewei Technologies.
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*/
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#include <linux/crash_core.h>
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#include <asm/cpufeature.h>
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#include <asm/memory.h>
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#include <asm/pgtable-hwdef.h>
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static inline u64 get_tcr_el1_t1sz(void);
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static inline u64 get_tcr_el1_t1sz(void)
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{
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return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET;
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}
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void arch_crash_save_vmcoreinfo(void)
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{
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VMCOREINFO_NUMBER(VA_BITS);
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/* Please note VMCOREINFO_NUMBER() uses "%d", not "%x" */
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vmcoreinfo_append_str("NUMBER(kimage_voffset)=0x%llx\n",
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kimage_voffset);
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vmcoreinfo_append_str("NUMBER(PHYS_OFFSET)=0x%llx\n",
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PHYS_OFFSET);
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vmcoreinfo_append_str("NUMBER(TCR_EL1_T1SZ)=0x%llx\n",
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get_tcr_el1_t1sz());
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vmcoreinfo_append_str("KERNELOFFSET=%lx\n", kaslr_offset());
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vmcoreinfo_append_str("NUMBER(KERNELPACMASK)=0x%llx\n",
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system_supports_address_auth() ?
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ptrauth_kernel_pac_mask() : 0);
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}
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