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ddc806b5c4
Currently when restoring the SVE state we supply the SVE vector length as an argument to sve_load_state() and the underlying macros. This becomes inconvenient with the addition of SME since we may need to restore any combination of SVE and SME vector lengths, and we already separately restore the vector length in the KVM code. We don't need to know the vector length during the actual register load since the SME load instructions can index into the data array for us. Refactor the interface so we explicitly set the vector length separately to restoring the SVE registers in preparation for adding SME support, no functional change should be involved. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20211019172247.3045838-9-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
88 lines
1.6 KiB
ArmAsm
88 lines
1.6 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* FP/SIMD state saving and restoring
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*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/fpsimdmacros.h>
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/*
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* Save the FP registers.
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*
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* x0 - pointer to struct fpsimd_state
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*/
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SYM_FUNC_START(fpsimd_save_state)
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fpsimd_save x0, 8
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ret
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SYM_FUNC_END(fpsimd_save_state)
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/*
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* Load the FP registers.
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*
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* x0 - pointer to struct fpsimd_state
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*/
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SYM_FUNC_START(fpsimd_load_state)
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fpsimd_restore x0, 8
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ret
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SYM_FUNC_END(fpsimd_load_state)
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#ifdef CONFIG_ARM64_SVE
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/*
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* Save the SVE state
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*
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* x0 - pointer to buffer for state
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* x1 - pointer to storage for FPSR
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* x2 - Save FFR if non-zero
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*/
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SYM_FUNC_START(sve_save_state)
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sve_save 0, x1, x2, 3
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ret
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SYM_FUNC_END(sve_save_state)
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/*
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* Load the SVE state
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*
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* x0 - pointer to buffer for state
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* x1 - pointer to storage for FPSR
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* x2 - Restore FFR if non-zero
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*/
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SYM_FUNC_START(sve_load_state)
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sve_load 0, x1, x2, 4
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ret
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SYM_FUNC_END(sve_load_state)
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SYM_FUNC_START(sve_get_vl)
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_sve_rdvl 0, 1
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ret
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SYM_FUNC_END(sve_get_vl)
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SYM_FUNC_START(sve_set_vq)
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sve_load_vq x0, x1, x2
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ret
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SYM_FUNC_END(sve_set_vq)
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/*
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* Zero all SVE registers but the first 128-bits of each vector
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*
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* VQ must already be configured by caller, any further updates of VQ
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* will need to ensure that the register state remains valid.
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*
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* x0 = include FFR?
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* x1 = VQ - 1
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*/
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SYM_FUNC_START(sve_flush_live)
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cbz x1, 1f // A VQ-1 of 0 is 128 bits so no extra Z state
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sve_flush_z
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1: sve_flush_p
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tbz x0, #0, 2f
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sve_flush_ffr
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2: ret
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SYM_FUNC_END(sve_flush_live)
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#endif /* CONFIG_ARM64_SVE */
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