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6cf61e061e
The never-ending entry.S refactoring continues, putting us in a much better place wrt compiler instrumentation whilst moving more of the code into C. * for-next/entry: arm64: idle: don't instrument idle code with KCOV arm64: entry: don't instrument entry code with KCOV arm64: entry: make NMI entry/exit functions static arm64: entry: split SDEI entry arm64: entry: split bad stack entry arm64: entry: fold el1_inv() into el1h_64_sync_handler() arm64: entry: handle all vectors with C arm64: entry: template the entry asm functions arm64: entry: improve bad_mode() arm64: entry: move bad_mode() to entry-common.c arm64: entry: consolidate EL1 exception returns arm64: entry: organise entry vectors consistently arm64: entry: organise entry handlers consistently arm64: entry: convert IRQ+FIQ handlers to C arm64: entry: add a call_on_irq_stack helper arm64: entry: move NMI preempt logic to C arm64: entry: move arm64_preempt_schedule_irq to entry-common.c arm64: entry: convert SError handlers to C arm64: entry: unmask IRQ+FIQ after EL0 handling arm64: remove redundant local_daif_mask() in bad_mode()
46 lines
918 B
C
46 lines
918 B
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Low-level idle sequences
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*/
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#include <linux/cpu.h>
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#include <linux/irqflags.h>
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#include <asm/barrier.h>
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#include <asm/cpuidle.h>
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#include <asm/cpufeature.h>
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#include <asm/sysreg.h>
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/*
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* cpu_do_idle()
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*
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* Idle the processor (wait for interrupt).
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*
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* If the CPU supports priority masking we must do additional work to
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* ensure that interrupts are not masked at the PMR (because the core will
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* not wake up if we block the wake up signal in the interrupt controller).
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*/
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void noinstr cpu_do_idle(void)
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{
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struct arm_cpuidle_irq_context context;
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arm_cpuidle_save_irq_context(&context);
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dsb(sy);
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wfi();
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arm_cpuidle_restore_irq_context(&context);
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}
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/*
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* This is our default idle handler.
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*/
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void noinstr arch_cpu_idle(void)
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{
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/*
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* This should do all the clock switching and wait for interrupt
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* tricks
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*/
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cpu_do_idle();
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raw_local_irq_enable();
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}
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