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![Wei Yongjun](/assets/img/avatar_default.png)
The dereference to 'pdata' should be moved below the NULL test. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
479 lines
11 KiB
C
479 lines
11 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "msm_gpu.h"
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#include "msm_gem.h"
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/*
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* Power Management:
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*/
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#ifdef CONFIG_MSM_BUS_SCALING
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#include <mach/board.h>
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#include <mach/kgsl.h>
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static void bs_init(struct msm_gpu *gpu, struct platform_device *pdev)
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{
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struct drm_device *dev = gpu->dev;
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struct kgsl_device_platform_data *pdata;
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if (!pdev) {
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dev_err(dev->dev, "could not find dtv pdata\n");
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return;
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}
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pdata = pdev->dev.platform_data;
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if (pdata->bus_scale_table) {
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gpu->bsc = msm_bus_scale_register_client(pdata->bus_scale_table);
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DBG("bus scale client: %08x", gpu->bsc);
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}
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}
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static void bs_fini(struct msm_gpu *gpu)
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{
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if (gpu->bsc) {
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msm_bus_scale_unregister_client(gpu->bsc);
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gpu->bsc = 0;
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}
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}
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static void bs_set(struct msm_gpu *gpu, int idx)
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{
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if (gpu->bsc) {
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DBG("set bus scaling: %d", idx);
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msm_bus_scale_client_update_request(gpu->bsc, idx);
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}
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}
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#else
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static void bs_init(struct msm_gpu *gpu, struct platform_device *pdev) {}
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static void bs_fini(struct msm_gpu *gpu) {}
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static void bs_set(struct msm_gpu *gpu, int idx) {}
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#endif
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static int enable_pwrrail(struct msm_gpu *gpu)
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{
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struct drm_device *dev = gpu->dev;
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int ret = 0;
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if (gpu->gpu_reg) {
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ret = regulator_enable(gpu->gpu_reg);
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if (ret) {
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dev_err(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
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return ret;
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}
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}
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if (gpu->gpu_cx) {
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ret = regulator_enable(gpu->gpu_cx);
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if (ret) {
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dev_err(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
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return ret;
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}
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}
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return 0;
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}
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static int disable_pwrrail(struct msm_gpu *gpu)
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{
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if (gpu->gpu_cx)
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regulator_disable(gpu->gpu_cx);
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if (gpu->gpu_reg)
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regulator_disable(gpu->gpu_reg);
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return 0;
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}
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static int enable_clk(struct msm_gpu *gpu)
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{
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struct clk *rate_clk = NULL;
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int i;
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/* NOTE: kgsl_pwrctrl_clk() ignores grp_clks[0].. */
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for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) {
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if (gpu->grp_clks[i]) {
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clk_prepare(gpu->grp_clks[i]);
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rate_clk = gpu->grp_clks[i];
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}
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}
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if (rate_clk && gpu->fast_rate)
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clk_set_rate(rate_clk, gpu->fast_rate);
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for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--)
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if (gpu->grp_clks[i])
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clk_enable(gpu->grp_clks[i]);
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return 0;
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}
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static int disable_clk(struct msm_gpu *gpu)
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{
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struct clk *rate_clk = NULL;
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int i;
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/* NOTE: kgsl_pwrctrl_clk() ignores grp_clks[0].. */
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for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) {
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if (gpu->grp_clks[i]) {
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clk_disable(gpu->grp_clks[i]);
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rate_clk = gpu->grp_clks[i];
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}
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}
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if (rate_clk && gpu->slow_rate)
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clk_set_rate(rate_clk, gpu->slow_rate);
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for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--)
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if (gpu->grp_clks[i])
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clk_unprepare(gpu->grp_clks[i]);
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return 0;
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}
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static int enable_axi(struct msm_gpu *gpu)
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{
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if (gpu->ebi1_clk)
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clk_prepare_enable(gpu->ebi1_clk);
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if (gpu->bus_freq)
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bs_set(gpu, gpu->bus_freq);
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return 0;
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}
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static int disable_axi(struct msm_gpu *gpu)
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{
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if (gpu->ebi1_clk)
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clk_disable_unprepare(gpu->ebi1_clk);
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if (gpu->bus_freq)
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bs_set(gpu, 0);
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return 0;
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}
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int msm_gpu_pm_resume(struct msm_gpu *gpu)
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{
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int ret;
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DBG("%s", gpu->name);
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ret = enable_pwrrail(gpu);
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if (ret)
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return ret;
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ret = enable_clk(gpu);
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if (ret)
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return ret;
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ret = enable_axi(gpu);
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if (ret)
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return ret;
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return 0;
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}
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int msm_gpu_pm_suspend(struct msm_gpu *gpu)
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{
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int ret;
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DBG("%s", gpu->name);
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ret = disable_axi(gpu);
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if (ret)
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return ret;
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ret = disable_clk(gpu);
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if (ret)
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return ret;
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ret = disable_pwrrail(gpu);
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if (ret)
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return ret;
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return 0;
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}
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/*
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* Hangcheck detection for locked gpu:
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*/
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static void recover_worker(struct work_struct *work)
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{
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struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
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struct drm_device *dev = gpu->dev;
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dev_err(dev->dev, "%s: hangcheck recover!\n", gpu->name);
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mutex_lock(&dev->struct_mutex);
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gpu->funcs->recover(gpu);
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mutex_unlock(&dev->struct_mutex);
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msm_gpu_retire(gpu);
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}
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static void hangcheck_timer_reset(struct msm_gpu *gpu)
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{
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DBG("%s", gpu->name);
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mod_timer(&gpu->hangcheck_timer,
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round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES));
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}
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static void hangcheck_handler(unsigned long data)
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{
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struct msm_gpu *gpu = (struct msm_gpu *)data;
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struct drm_device *dev = gpu->dev;
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struct msm_drm_private *priv = dev->dev_private;
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uint32_t fence = gpu->funcs->last_fence(gpu);
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if (fence != gpu->hangcheck_fence) {
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/* some progress has been made.. ya! */
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gpu->hangcheck_fence = fence;
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} else if (fence < gpu->submitted_fence) {
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/* no progress and not done.. hung! */
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gpu->hangcheck_fence = fence;
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dev_err(dev->dev, "%s: hangcheck detected gpu lockup!\n",
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gpu->name);
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dev_err(dev->dev, "%s: completed fence: %u\n",
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gpu->name, fence);
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dev_err(dev->dev, "%s: submitted fence: %u\n",
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gpu->name, gpu->submitted_fence);
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queue_work(priv->wq, &gpu->recover_work);
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}
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/* if still more pending work, reset the hangcheck timer: */
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if (gpu->submitted_fence > gpu->hangcheck_fence)
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hangcheck_timer_reset(gpu);
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/* workaround for missing irq: */
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queue_work(priv->wq, &gpu->retire_work);
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}
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/*
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* Cmdstream submission/retirement:
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*/
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static void retire_worker(struct work_struct *work)
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{
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struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
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struct drm_device *dev = gpu->dev;
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uint32_t fence = gpu->funcs->last_fence(gpu);
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mutex_lock(&dev->struct_mutex);
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while (!list_empty(&gpu->active_list)) {
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struct msm_gem_object *obj;
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obj = list_first_entry(&gpu->active_list,
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struct msm_gem_object, mm_list);
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if ((obj->read_fence <= fence) &&
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(obj->write_fence <= fence)) {
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/* move to inactive: */
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msm_gem_move_to_inactive(&obj->base);
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msm_gem_put_iova(&obj->base, gpu->id);
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drm_gem_object_unreference(&obj->base);
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} else {
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break;
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}
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}
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msm_update_fence(gpu->dev, fence);
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mutex_unlock(&dev->struct_mutex);
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}
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/* call from irq handler to schedule work to retire bo's */
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void msm_gpu_retire(struct msm_gpu *gpu)
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{
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struct msm_drm_private *priv = gpu->dev->dev_private;
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queue_work(priv->wq, &gpu->retire_work);
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}
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/* add bo's to gpu's ring, and kick gpu: */
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int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
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struct msm_file_private *ctx)
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{
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struct drm_device *dev = gpu->dev;
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struct msm_drm_private *priv = dev->dev_private;
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int i, ret;
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mutex_lock(&dev->struct_mutex);
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submit->fence = ++priv->next_fence;
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gpu->submitted_fence = submit->fence;
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ret = gpu->funcs->submit(gpu, submit, ctx);
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priv->lastctx = ctx;
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for (i = 0; i < submit->nr_bos; i++) {
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struct msm_gem_object *msm_obj = submit->bos[i].obj;
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/* can't happen yet.. but when we add 2d support we'll have
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* to deal w/ cross-ring synchronization:
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*/
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WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu));
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if (!is_active(msm_obj)) {
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uint32_t iova;
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/* ring takes a reference to the bo and iova: */
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drm_gem_object_reference(&msm_obj->base);
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msm_gem_get_iova_locked(&msm_obj->base,
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submit->gpu->id, &iova);
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}
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if (submit->bos[i].flags & MSM_SUBMIT_BO_READ)
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msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence);
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if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE)
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msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence);
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}
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hangcheck_timer_reset(gpu);
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mutex_unlock(&dev->struct_mutex);
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return ret;
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}
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/*
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* Init/Cleanup:
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*/
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static irqreturn_t irq_handler(int irq, void *data)
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{
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struct msm_gpu *gpu = data;
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return gpu->funcs->irq(gpu);
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}
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static const char *clk_names[] = {
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"src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk",
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};
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int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
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struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
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const char *name, const char *ioname, const char *irqname, int ringsz)
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{
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int i, ret;
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gpu->dev = drm;
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gpu->funcs = funcs;
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gpu->name = name;
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INIT_LIST_HEAD(&gpu->active_list);
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INIT_WORK(&gpu->retire_work, retire_worker);
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INIT_WORK(&gpu->recover_work, recover_worker);
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setup_timer(&gpu->hangcheck_timer, hangcheck_handler,
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(unsigned long)gpu);
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BUG_ON(ARRAY_SIZE(clk_names) != ARRAY_SIZE(gpu->grp_clks));
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/* Map registers: */
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gpu->mmio = msm_ioremap(pdev, ioname, name);
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if (IS_ERR(gpu->mmio)) {
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ret = PTR_ERR(gpu->mmio);
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goto fail;
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}
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/* Get Interrupt: */
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gpu->irq = platform_get_irq_byname(pdev, irqname);
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if (gpu->irq < 0) {
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ret = gpu->irq;
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dev_err(drm->dev, "failed to get irq: %d\n", ret);
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goto fail;
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}
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ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
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IRQF_TRIGGER_HIGH, gpu->name, gpu);
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if (ret) {
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dev_err(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
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goto fail;
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}
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/* Acquire clocks: */
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for (i = 0; i < ARRAY_SIZE(clk_names); i++) {
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gpu->grp_clks[i] = devm_clk_get(&pdev->dev, clk_names[i]);
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DBG("grp_clks[%s]: %p", clk_names[i], gpu->grp_clks[i]);
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if (IS_ERR(gpu->grp_clks[i]))
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gpu->grp_clks[i] = NULL;
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}
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gpu->ebi1_clk = devm_clk_get(&pdev->dev, "bus_clk");
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DBG("ebi1_clk: %p", gpu->ebi1_clk);
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if (IS_ERR(gpu->ebi1_clk))
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gpu->ebi1_clk = NULL;
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/* Acquire regulators: */
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gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
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DBG("gpu_reg: %p", gpu->gpu_reg);
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if (IS_ERR(gpu->gpu_reg))
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gpu->gpu_reg = NULL;
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gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
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DBG("gpu_cx: %p", gpu->gpu_cx);
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if (IS_ERR(gpu->gpu_cx))
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gpu->gpu_cx = NULL;
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/* Setup IOMMU.. eventually we will (I think) do this once per context
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* and have separate page tables per context. For now, to keep things
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* simple and to get something working, just use a single address space:
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*/
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gpu->iommu = iommu_domain_alloc(&platform_bus_type);
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if (!gpu->iommu) {
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dev_err(drm->dev, "failed to allocate IOMMU\n");
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ret = -ENOMEM;
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goto fail;
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}
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gpu->id = msm_register_iommu(drm, gpu->iommu);
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/* Create ringbuffer: */
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gpu->rb = msm_ringbuffer_new(gpu, ringsz);
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if (IS_ERR(gpu->rb)) {
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ret = PTR_ERR(gpu->rb);
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gpu->rb = NULL;
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dev_err(drm->dev, "could not create ringbuffer: %d\n", ret);
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goto fail;
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}
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ret = msm_gem_get_iova_locked(gpu->rb->bo, gpu->id, &gpu->rb_iova);
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if (ret) {
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gpu->rb_iova = 0;
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dev_err(drm->dev, "could not map ringbuffer: %d\n", ret);
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goto fail;
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}
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bs_init(gpu, pdev);
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return 0;
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fail:
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return ret;
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}
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void msm_gpu_cleanup(struct msm_gpu *gpu)
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{
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DBG("%s", gpu->name);
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WARN_ON(!list_empty(&gpu->active_list));
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bs_fini(gpu);
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if (gpu->rb) {
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if (gpu->rb_iova)
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msm_gem_put_iova(gpu->rb->bo, gpu->id);
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msm_ringbuffer_destroy(gpu->rb);
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}
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if (gpu->iommu)
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iommu_domain_free(gpu->iommu);
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}
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