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![Dave Airlie](/assets/img/avatar_default.png)
Alex writes: This is the radeon drm-next request. Big changes include: - support for dpm on CIK parts - support for ASPM on CIK parts - support for berlin GPUs - major ring handling cleanup - remove the old 3D blit code for bo moves in favor of CP DMA or sDMA - lots of bug fixes [airlied: fix up a bunch of conflicts from drm_order removal] * 'drm-next-3.12' of git://people.freedesktop.org/~agd5f/linux: (898 commits) drm/radeon/dpm: make sure dc performance level limits are valid (CI) drm/radeon/dpm: make sure dc performance level limits are valid (BTC-SI) (v2) drm/radeon: gcc fixes for extended dpm tables drm/radeon: gcc fixes for kb/kv dpm drm/radeon: gcc fixes for ci dpm drm/radeon: gcc fixes for si dpm drm/radeon: gcc fixes for ni dpm drm/radeon: gcc fixes for trinity dpm drm/radeon: gcc fixes for sumo dpm drm/radeonn: gcc fixes for rv7xx/eg/btc dpm drm/radeon: gcc fixes for rv6xx dpm drm/radeon: gcc fixes for radeon_atombios.c drm/radeon: enable UVD interrupts on CIK drm/radeon: fix init ordering for r600+ drm/radeon/dpm: only need to reprogram uvd if uvd pg is enabled drm/radeon: check the return value of uvd_v1_0_start in uvd_v1_0_init drm/radeon: split out radeon_uvd_resume from uvd_v4_2_resume radeon kms: fix uninitialised hotplug work usage in r100_irq_process() drm/radeon/audio: set up the sads on DCE3.2 asics drm/radeon: fix handling of variable sized arrays for router objects ... Conflicts: drivers/gpu/drm/i915/i915_dma.c drivers/gpu/drm/i915/i915_gem_dmabuf.c drivers/gpu/drm/i915/intel_pm.c drivers/gpu/drm/radeon/cik.c drivers/gpu/drm/radeon/ni.c drivers/gpu/drm/radeon/r600.c
497 lines
13 KiB
C
497 lines
13 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "r600d.h"
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u32 r600_gpu_check_soft_reset(struct radeon_device *rdev);
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/*
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* DMA
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* Starting with R600, the GPU has an asynchronous
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* DMA engine. The programming model is very similar
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* to the 3D engine (ring buffer, IBs, etc.), but the
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* DMA controller has it's own packet format that is
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* different form the PM4 format used by the 3D engine.
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* It supports copying data, writing embedded data,
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* solid fills, and a number of other things. It also
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* has support for tiling/detiling of buffers.
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*/
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/**
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* r600_dma_get_rptr - get the current read pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon ring pointer
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*
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* Get the current rptr from the hardware (r6xx+).
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*/
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uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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return (radeon_ring_generic_get_rptr(rdev, ring) & 0x3fffc) >> 2;
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}
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/**
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* r600_dma_get_wptr - get the current write pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon ring pointer
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*
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* Get the current wptr from the hardware (r6xx+).
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*/
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uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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return (RREG32(ring->wptr_reg) & 0x3fffc) >> 2;
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}
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/**
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* r600_dma_set_wptr - commit the write pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon ring pointer
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*
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* Write the wptr back to the hardware (r6xx+).
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*/
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void r600_dma_set_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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WREG32(ring->wptr_reg, (ring->wptr << 2) & 0x3fffc);
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}
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/**
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* r600_dma_stop - stop the async dma engine
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*
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* @rdev: radeon_device pointer
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*
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* Stop the async dma engine (r6xx-evergreen).
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*/
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void r600_dma_stop(struct radeon_device *rdev)
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{
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u32 rb_cntl = RREG32(DMA_RB_CNTL);
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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rb_cntl &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL, rb_cntl);
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rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
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}
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/**
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* r600_dma_resume - setup and start the async dma engine
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*
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* @rdev: radeon_device pointer
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*
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* Set up the DMA ring buffer and enable it. (r6xx-evergreen).
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* Returns 0 for success, error for failure.
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*/
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int r600_dma_resume(struct radeon_device *rdev)
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{
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struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
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u32 rb_cntl, dma_cntl, ib_cntl;
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u32 rb_bufsz;
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int r;
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/* Reset dma */
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if (rdev->family >= CHIP_RV770)
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WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
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else
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WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
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RREG32(SRBM_SOFT_RESET);
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udelay(50);
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WREG32(SRBM_SOFT_RESET, 0);
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WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
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WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
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/* Set ring buffer size in dwords */
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rb_bufsz = order_base_2(ring->ring_size / 4);
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rb_cntl = rb_bufsz << 1;
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#ifdef __BIG_ENDIAN
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rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
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#endif
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WREG32(DMA_RB_CNTL, rb_cntl);
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/* Initialize the ring buffer's read and write pointers */
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WREG32(DMA_RB_RPTR, 0);
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WREG32(DMA_RB_WPTR, 0);
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/* set the wb address whether it's enabled or not */
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WREG32(DMA_RB_RPTR_ADDR_HI,
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upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
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WREG32(DMA_RB_RPTR_ADDR_LO,
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((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
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if (rdev->wb.enabled)
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rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
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WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
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/* enable DMA IBs */
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ib_cntl = DMA_IB_ENABLE;
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#ifdef __BIG_ENDIAN
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ib_cntl |= DMA_IB_SWAP_ENABLE;
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#endif
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WREG32(DMA_IB_CNTL, ib_cntl);
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dma_cntl = RREG32(DMA_CNTL);
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dma_cntl &= ~CTXEMPTY_INT_ENABLE;
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WREG32(DMA_CNTL, dma_cntl);
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if (rdev->family >= CHIP_RV770)
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WREG32(DMA_MODE, 1);
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ring->wptr = 0;
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WREG32(DMA_RB_WPTR, ring->wptr << 2);
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ring->rptr = RREG32(DMA_RB_RPTR) >> 2;
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WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
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ring->ready = true;
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r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
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if (r) {
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ring->ready = false;
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return r;
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}
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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return 0;
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}
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/**
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* r600_dma_fini - tear down the async dma engine
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*
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* @rdev: radeon_device pointer
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*
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* Stop the async dma engine and free the ring (r6xx-evergreen).
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*/
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void r600_dma_fini(struct radeon_device *rdev)
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{
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r600_dma_stop(rdev);
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radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
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}
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/**
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* r600_dma_is_lockup - Check if the DMA engine is locked up
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring structure holding ring information
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*
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* Check if the async DMA engine is locked up.
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* Returns true if the engine appears to be locked up, false if not.
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*/
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bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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u32 reset_mask = r600_gpu_check_soft_reset(rdev);
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if (!(reset_mask & RADEON_RESET_DMA)) {
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radeon_ring_lockup_update(ring);
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return false;
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}
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/* force ring activities */
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radeon_ring_force_activity(rdev, ring);
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return radeon_ring_test_lockup(rdev, ring);
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}
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/**
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* r600_dma_ring_test - simple async dma engine test
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring structure holding ring information
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*
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* Test the DMA engine by writing using it to write an
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* value to memory. (r6xx-SI).
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* Returns 0 for success, error for failure.
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*/
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int r600_dma_ring_test(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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unsigned i;
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int r;
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void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
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u32 tmp;
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if (!ptr) {
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DRM_ERROR("invalid vram scratch pointer\n");
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return -EINVAL;
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}
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tmp = 0xCAFEDEAD;
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writel(tmp, ptr);
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r = radeon_ring_lock(rdev, ring, 4);
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if (r) {
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DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
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return r;
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}
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
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radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
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radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
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radeon_ring_write(ring, 0xDEADBEEF);
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radeon_ring_unlock_commit(rdev, ring);
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for (i = 0; i < rdev->usec_timeout; i++) {
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tmp = readl(ptr);
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if (tmp == 0xDEADBEEF)
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break;
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DRM_UDELAY(1);
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}
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if (i < rdev->usec_timeout) {
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DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
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} else {
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DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
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ring->idx, tmp);
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r = -EINVAL;
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}
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return r;
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}
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/**
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* r600_dma_fence_ring_emit - emit a fence on the DMA ring
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*
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* @rdev: radeon_device pointer
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* @fence: radeon fence object
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*
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* Add a DMA fence packet to the ring to write
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* the fence seq number and DMA trap packet to generate
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* an interrupt if needed (r6xx-r7xx).
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*/
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void r600_dma_fence_ring_emit(struct radeon_device *rdev,
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struct radeon_fence *fence)
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{
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struct radeon_ring *ring = &rdev->ring[fence->ring];
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u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
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/* write the fence */
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
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radeon_ring_write(ring, addr & 0xfffffffc);
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radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
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radeon_ring_write(ring, lower_32_bits(fence->seq));
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/* generate an interrupt */
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
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}
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/**
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* r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring structure holding ring information
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* @semaphore: radeon semaphore object
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* @emit_wait: wait or signal semaphore
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*
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* Add a DMA semaphore packet to the ring wait on or signal
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* other rings (r6xx-SI).
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*/
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void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
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struct radeon_ring *ring,
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struct radeon_semaphore *semaphore,
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bool emit_wait)
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{
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u64 addr = semaphore->gpu_addr;
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u32 s = emit_wait ? 0 : 1;
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
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radeon_ring_write(ring, addr & 0xfffffffc);
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radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
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}
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/**
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* r600_dma_ib_test - test an IB on the DMA engine
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring structure holding ring information
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*
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* Test a simple IB in the DMA ring (r6xx-SI).
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* Returns 0 on success, error on failure.
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*/
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int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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struct radeon_ib ib;
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unsigned i;
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int r;
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void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
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u32 tmp = 0;
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if (!ptr) {
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DRM_ERROR("invalid vram scratch pointer\n");
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return -EINVAL;
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}
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tmp = 0xCAFEDEAD;
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writel(tmp, ptr);
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r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
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if (r) {
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DRM_ERROR("radeon: failed to get ib (%d).\n", r);
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return r;
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}
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ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
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ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
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ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
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ib.ptr[3] = 0xDEADBEEF;
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ib.length_dw = 4;
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r = radeon_ib_schedule(rdev, &ib, NULL);
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if (r) {
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radeon_ib_free(rdev, &ib);
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DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
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return r;
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}
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r = radeon_fence_wait(ib.fence, false);
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if (r) {
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DRM_ERROR("radeon: fence wait failed (%d).\n", r);
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return r;
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}
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for (i = 0; i < rdev->usec_timeout; i++) {
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tmp = readl(ptr);
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if (tmp == 0xDEADBEEF)
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break;
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DRM_UDELAY(1);
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}
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if (i < rdev->usec_timeout) {
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DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
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} else {
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DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
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r = -EINVAL;
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}
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radeon_ib_free(rdev, &ib);
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return r;
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}
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/**
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* r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
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*
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* @rdev: radeon_device pointer
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* @ib: IB object to schedule
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*
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* Schedule an IB in the DMA ring (r6xx-r7xx).
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*/
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void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
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{
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struct radeon_ring *ring = &rdev->ring[ib->ring];
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if (rdev->wb.enabled) {
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u32 next_rptr = ring->wptr + 4;
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while ((next_rptr & 7) != 5)
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next_rptr++;
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next_rptr += 3;
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
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radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
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radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
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radeon_ring_write(ring, next_rptr);
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}
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/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
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* Pad as necessary with NOPs.
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*/
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while ((ring->wptr & 7) != 5)
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
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radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
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radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
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}
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/**
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* r600_copy_dma - copy pages using the DMA engine
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*
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* @rdev: radeon_device pointer
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* @src_offset: src GPU address
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* @dst_offset: dst GPU address
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* @num_gpu_pages: number of GPU pages to xfer
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* @fence: radeon fence object
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*
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* Copy GPU paging using the DMA engine (r6xx).
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* Used by the radeon ttm implementation to move pages if
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* registered as the asic copy callback.
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*/
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int r600_copy_dma(struct radeon_device *rdev,
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uint64_t src_offset, uint64_t dst_offset,
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unsigned num_gpu_pages,
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struct radeon_fence **fence)
|
|
{
|
|
struct radeon_semaphore *sem = NULL;
|
|
int ring_index = rdev->asic->copy.dma_ring_index;
|
|
struct radeon_ring *ring = &rdev->ring[ring_index];
|
|
u32 size_in_dw, cur_size_in_dw;
|
|
int i, num_loops;
|
|
int r = 0;
|
|
|
|
r = radeon_semaphore_create(rdev, &sem);
|
|
if (r) {
|
|
DRM_ERROR("radeon: moving bo (%d).\n", r);
|
|
return r;
|
|
}
|
|
|
|
size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
|
|
num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE);
|
|
r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
|
|
if (r) {
|
|
DRM_ERROR("radeon: moving bo (%d).\n", r);
|
|
radeon_semaphore_free(rdev, &sem, NULL);
|
|
return r;
|
|
}
|
|
|
|
if (radeon_fence_need_sync(*fence, ring->idx)) {
|
|
radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
|
|
ring->idx);
|
|
radeon_fence_note_sync(*fence, ring->idx);
|
|
} else {
|
|
radeon_semaphore_free(rdev, &sem, NULL);
|
|
}
|
|
|
|
for (i = 0; i < num_loops; i++) {
|
|
cur_size_in_dw = size_in_dw;
|
|
if (cur_size_in_dw > 0xFFFE)
|
|
cur_size_in_dw = 0xFFFE;
|
|
size_in_dw -= cur_size_in_dw;
|
|
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
|
|
radeon_ring_write(ring, dst_offset & 0xfffffffc);
|
|
radeon_ring_write(ring, src_offset & 0xfffffffc);
|
|
radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
|
|
(upper_32_bits(src_offset) & 0xff)));
|
|
src_offset += cur_size_in_dw * 4;
|
|
dst_offset += cur_size_in_dw * 4;
|
|
}
|
|
|
|
r = radeon_fence_emit(rdev, fence, ring->idx);
|
|
if (r) {
|
|
radeon_ring_unlock_undo(rdev, ring);
|
|
return r;
|
|
}
|
|
|
|
radeon_ring_unlock_commit(rdev, ring);
|
|
radeon_semaphore_free(rdev, &sem, *fence);
|
|
|
|
return r;
|
|
}
|