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The memory controller found on Tegra186 is different in some respects to its predecessors. Most notably it no longer implements an SMMU, but does assign ARM SMMU stream IDs for each memory client instead. Provide a driver that programs these registers so that memory clients can translate addresses via the ARM SMMU. Signed-off-by: Thierry Reding <treding@nvidia.com>
13 lines
445 B
Makefile
13 lines
445 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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tegra-mc-y := mc.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
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obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
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obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
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obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
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