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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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ee50d07c9f
The Ocelot switchdev driver and the Felix DSA one need it for different reasons. Felix (or at least the VSC9959 instantiation in NXP LS1028A) is integrated with the traditional NXP Layerscape PCS design which does not support runtime configuration of SerDes protocol. So it needs to pre-validate the phy-mode from the device tree and prevent PHYLINK from attempting to change it. For this, it needs to cache it in a private variable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
545 lines
14 KiB
C
545 lines
14 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/* Copyright (c) 2017 Microsemi Corporation
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*/
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#ifndef _SOC_MSCC_OCELOT_H
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#define _SOC_MSCC_OCELOT_H
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#include <linux/ptp_clock_kernel.h>
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#include <linux/net_tstamp.h>
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#include <linux/if_vlan.h>
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#include <linux/regmap.h>
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#include <net/dsa.h>
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#define IFH_INJ_BYPASS BIT(31)
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#define IFH_INJ_POP_CNT_DISABLE (3 << 28)
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#define IFH_TAG_TYPE_C 0
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#define IFH_TAG_TYPE_S 1
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#define IFH_REW_OP_NOOP 0x0
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#define IFH_REW_OP_DSCP 0x1
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#define IFH_REW_OP_ONE_STEP_PTP 0x2
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#define IFH_REW_OP_TWO_STEP_PTP 0x3
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#define IFH_REW_OP_ORIGIN_PTP 0x5
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#define OCELOT_TAG_LEN 16
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#define OCELOT_SHORT_PREFIX_LEN 4
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#define OCELOT_LONG_PREFIX_LEN 16
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#define OCELOT_SPEED_2500 0
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#define OCELOT_SPEED_1000 1
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#define OCELOT_SPEED_100 2
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#define OCELOT_SPEED_10 3
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#define TARGET_OFFSET 24
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#define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
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#define REG(reg, offset) [reg & REG_MASK] = offset
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#define REG_RESERVED_ADDR 0xffffffff
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#define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
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enum ocelot_target {
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ANA = 1,
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QS,
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QSYS,
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REW,
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SYS,
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S2,
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HSIO,
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PTP,
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GCB,
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TARGET_MAX,
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};
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enum ocelot_reg {
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ANA_ADVLEARN = ANA << TARGET_OFFSET,
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ANA_VLANMASK,
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ANA_PORT_B_DOMAIN,
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ANA_ANAGEFIL,
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ANA_ANEVENTS,
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ANA_STORMLIMIT_BURST,
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ANA_STORMLIMIT_CFG,
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ANA_ISOLATED_PORTS,
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ANA_COMMUNITY_PORTS,
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ANA_AUTOAGE,
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ANA_MACTOPTIONS,
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ANA_LEARNDISC,
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ANA_AGENCTRL,
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ANA_MIRRORPORTS,
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ANA_EMIRRORPORTS,
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ANA_FLOODING,
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ANA_FLOODING_IPMC,
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ANA_SFLOW_CFG,
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ANA_PORT_MODE,
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ANA_CUT_THRU_CFG,
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ANA_PGID_PGID,
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ANA_TABLES_ANMOVED,
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ANA_TABLES_MACHDATA,
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ANA_TABLES_MACLDATA,
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ANA_TABLES_STREAMDATA,
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ANA_TABLES_MACACCESS,
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ANA_TABLES_MACTINDX,
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ANA_TABLES_VLANACCESS,
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ANA_TABLES_VLANTIDX,
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ANA_TABLES_ISDXACCESS,
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ANA_TABLES_ISDXTIDX,
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ANA_TABLES_ENTRYLIM,
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ANA_TABLES_PTP_ID_HIGH,
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ANA_TABLES_PTP_ID_LOW,
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ANA_TABLES_STREAMACCESS,
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ANA_TABLES_STREAMTIDX,
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ANA_TABLES_SEQ_HISTORY,
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ANA_TABLES_SEQ_MASK,
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ANA_TABLES_SFID_MASK,
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ANA_TABLES_SFIDACCESS,
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ANA_TABLES_SFIDTIDX,
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ANA_MSTI_STATE,
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ANA_OAM_UPM_LM_CNT,
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ANA_SG_ACCESS_CTRL,
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ANA_SG_CONFIG_REG_1,
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ANA_SG_CONFIG_REG_2,
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ANA_SG_CONFIG_REG_3,
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ANA_SG_CONFIG_REG_4,
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ANA_SG_CONFIG_REG_5,
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ANA_SG_GCL_GS_CONFIG,
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ANA_SG_GCL_TI_CONFIG,
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ANA_SG_STATUS_REG_1,
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ANA_SG_STATUS_REG_2,
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ANA_SG_STATUS_REG_3,
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ANA_PORT_VLAN_CFG,
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ANA_PORT_DROP_CFG,
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ANA_PORT_QOS_CFG,
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ANA_PORT_VCAP_CFG,
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ANA_PORT_VCAP_S1_KEY_CFG,
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ANA_PORT_VCAP_S2_CFG,
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ANA_PORT_PCP_DEI_MAP,
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ANA_PORT_CPU_FWD_CFG,
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ANA_PORT_CPU_FWD_BPDU_CFG,
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ANA_PORT_CPU_FWD_GARP_CFG,
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ANA_PORT_CPU_FWD_CCM_CFG,
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ANA_PORT_PORT_CFG,
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ANA_PORT_POL_CFG,
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ANA_PORT_PTP_CFG,
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ANA_PORT_PTP_DLY1_CFG,
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ANA_PORT_PTP_DLY2_CFG,
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ANA_PORT_SFID_CFG,
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ANA_PFC_PFC_CFG,
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ANA_PFC_PFC_TIMER,
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ANA_IPT_OAM_MEP_CFG,
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ANA_IPT_IPT,
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ANA_PPT_PPT,
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ANA_FID_MAP_FID_MAP,
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ANA_AGGR_CFG,
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ANA_CPUQ_CFG,
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ANA_CPUQ_CFG2,
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ANA_CPUQ_8021_CFG,
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ANA_DSCP_CFG,
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ANA_DSCP_REWR_CFG,
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ANA_VCAP_RNG_TYPE_CFG,
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ANA_VCAP_RNG_VAL_CFG,
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ANA_VRAP_CFG,
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ANA_VRAP_HDR_DATA,
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ANA_VRAP_HDR_MASK,
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ANA_DISCARD_CFG,
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ANA_FID_CFG,
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ANA_POL_PIR_CFG,
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ANA_POL_CIR_CFG,
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ANA_POL_MODE_CFG,
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ANA_POL_PIR_STATE,
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ANA_POL_CIR_STATE,
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ANA_POL_STATE,
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ANA_POL_FLOWC,
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ANA_POL_HYST,
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ANA_POL_MISC_CFG,
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QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
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QS_XTR_RD,
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QS_XTR_FRM_PRUNING,
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QS_XTR_FLUSH,
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QS_XTR_DATA_PRESENT,
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QS_XTR_CFG,
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QS_INJ_GRP_CFG,
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QS_INJ_WR,
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QS_INJ_CTRL,
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QS_INJ_STATUS,
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QS_INJ_ERR,
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QS_INH_DBG,
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QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
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QSYS_SWITCH_PORT_MODE,
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QSYS_STAT_CNT_CFG,
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QSYS_EEE_CFG,
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QSYS_EEE_THRES,
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QSYS_IGR_NO_SHARING,
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QSYS_EGR_NO_SHARING,
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QSYS_SW_STATUS,
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QSYS_EXT_CPU_CFG,
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QSYS_PAD_CFG,
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QSYS_CPU_GROUP_MAP,
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QSYS_QMAP,
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QSYS_ISDX_SGRP,
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QSYS_TIMED_FRAME_ENTRY,
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QSYS_TFRM_MISC,
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QSYS_TFRM_PORT_DLY,
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QSYS_TFRM_TIMER_CFG_1,
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QSYS_TFRM_TIMER_CFG_2,
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QSYS_TFRM_TIMER_CFG_3,
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QSYS_TFRM_TIMER_CFG_4,
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QSYS_TFRM_TIMER_CFG_5,
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QSYS_TFRM_TIMER_CFG_6,
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QSYS_TFRM_TIMER_CFG_7,
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QSYS_TFRM_TIMER_CFG_8,
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QSYS_RED_PROFILE,
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QSYS_RES_QOS_MODE,
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QSYS_RES_CFG,
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QSYS_RES_STAT,
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QSYS_EGR_DROP_MODE,
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QSYS_EQ_CTRL,
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QSYS_EVENTS_CORE,
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QSYS_QMAXSDU_CFG_0,
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QSYS_QMAXSDU_CFG_1,
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QSYS_QMAXSDU_CFG_2,
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QSYS_QMAXSDU_CFG_3,
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QSYS_QMAXSDU_CFG_4,
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QSYS_QMAXSDU_CFG_5,
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QSYS_QMAXSDU_CFG_6,
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QSYS_QMAXSDU_CFG_7,
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QSYS_PREEMPTION_CFG,
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QSYS_CIR_CFG,
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QSYS_EIR_CFG,
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QSYS_SE_CFG,
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QSYS_SE_DWRR_CFG,
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QSYS_SE_CONNECT,
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QSYS_SE_DLB_SENSE,
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QSYS_CIR_STATE,
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QSYS_EIR_STATE,
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QSYS_SE_STATE,
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QSYS_HSCH_MISC_CFG,
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QSYS_TAG_CONFIG,
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QSYS_TAS_PARAM_CFG_CTRL,
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QSYS_PORT_MAX_SDU,
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QSYS_PARAM_CFG_REG_1,
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QSYS_PARAM_CFG_REG_2,
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QSYS_PARAM_CFG_REG_3,
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QSYS_PARAM_CFG_REG_4,
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QSYS_PARAM_CFG_REG_5,
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QSYS_GCL_CFG_REG_1,
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QSYS_GCL_CFG_REG_2,
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QSYS_PARAM_STATUS_REG_1,
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QSYS_PARAM_STATUS_REG_2,
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QSYS_PARAM_STATUS_REG_3,
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QSYS_PARAM_STATUS_REG_4,
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QSYS_PARAM_STATUS_REG_5,
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QSYS_PARAM_STATUS_REG_6,
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QSYS_PARAM_STATUS_REG_7,
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QSYS_PARAM_STATUS_REG_8,
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QSYS_PARAM_STATUS_REG_9,
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QSYS_GCL_STATUS_REG_1,
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QSYS_GCL_STATUS_REG_2,
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REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
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REW_TAG_CFG,
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REW_PORT_CFG,
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REW_DSCP_CFG,
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REW_PCP_DEI_QOS_MAP_CFG,
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REW_PTP_CFG,
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REW_PTP_DLY1_CFG,
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REW_RED_TAG_CFG,
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REW_DSCP_REMAP_DP1_CFG,
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REW_DSCP_REMAP_CFG,
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REW_STAT_CFG,
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REW_REW_STICKY,
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REW_PPT,
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SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
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SYS_COUNT_RX_UNICAST,
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SYS_COUNT_RX_MULTICAST,
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SYS_COUNT_RX_BROADCAST,
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SYS_COUNT_RX_SHORTS,
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SYS_COUNT_RX_FRAGMENTS,
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SYS_COUNT_RX_JABBERS,
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SYS_COUNT_RX_CRC_ALIGN_ERRS,
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SYS_COUNT_RX_SYM_ERRS,
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SYS_COUNT_RX_64,
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SYS_COUNT_RX_65_127,
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SYS_COUNT_RX_128_255,
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SYS_COUNT_RX_256_1023,
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SYS_COUNT_RX_1024_1526,
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SYS_COUNT_RX_1527_MAX,
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SYS_COUNT_RX_PAUSE,
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SYS_COUNT_RX_CONTROL,
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SYS_COUNT_RX_LONGS,
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SYS_COUNT_RX_CLASSIFIED_DROPS,
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SYS_COUNT_TX_OCTETS,
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SYS_COUNT_TX_UNICAST,
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SYS_COUNT_TX_MULTICAST,
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SYS_COUNT_TX_BROADCAST,
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SYS_COUNT_TX_COLLISION,
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SYS_COUNT_TX_DROPS,
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SYS_COUNT_TX_PAUSE,
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SYS_COUNT_TX_64,
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SYS_COUNT_TX_65_127,
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SYS_COUNT_TX_128_511,
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SYS_COUNT_TX_512_1023,
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SYS_COUNT_TX_1024_1526,
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SYS_COUNT_TX_1527_MAX,
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SYS_COUNT_TX_AGING,
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SYS_RESET_CFG,
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SYS_SR_ETYPE_CFG,
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SYS_VLAN_ETYPE_CFG,
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SYS_PORT_MODE,
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SYS_FRONT_PORT_MODE,
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SYS_FRM_AGING,
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SYS_STAT_CFG,
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SYS_SW_STATUS,
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SYS_MISC_CFG,
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SYS_REW_MAC_HIGH_CFG,
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SYS_REW_MAC_LOW_CFG,
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SYS_TIMESTAMP_OFFSET,
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SYS_CMID,
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SYS_PAUSE_CFG,
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SYS_PAUSE_TOT_CFG,
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SYS_ATOP,
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SYS_ATOP_TOT_CFG,
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SYS_MAC_FC_CFG,
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SYS_MMGT,
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SYS_MMGT_FAST,
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SYS_EVENTS_DIF,
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SYS_EVENTS_CORE,
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SYS_CNT,
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SYS_PTP_STATUS,
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SYS_PTP_TXSTAMP,
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SYS_PTP_NXT,
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SYS_PTP_CFG,
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SYS_RAM_INIT,
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SYS_CM_ADDR,
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SYS_CM_DATA_WR,
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SYS_CM_DATA_RD,
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SYS_CM_OP,
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SYS_CM_DATA,
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S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
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S2_CORE_MV_CFG,
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S2_CACHE_ENTRY_DAT,
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S2_CACHE_MASK_DAT,
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S2_CACHE_ACTION_DAT,
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S2_CACHE_CNT_DAT,
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S2_CACHE_TG_DAT,
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PTP_PIN_CFG = PTP << TARGET_OFFSET,
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PTP_PIN_TOD_SEC_MSB,
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PTP_PIN_TOD_SEC_LSB,
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PTP_PIN_TOD_NSEC,
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PTP_CFG_MISC,
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PTP_CLK_CFG_ADJ_CFG,
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PTP_CLK_CFG_ADJ_FREQ,
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GCB_SOFT_RST = GCB << TARGET_OFFSET,
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};
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enum ocelot_regfield {
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ANA_ADVLEARN_VLAN_CHK,
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ANA_ADVLEARN_LEARN_MIRROR,
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ANA_ANEVENTS_FLOOD_DISCARD,
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ANA_ANEVENTS_MSTI_DROP,
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ANA_ANEVENTS_ACLKILL,
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ANA_ANEVENTS_ACLUSED,
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ANA_ANEVENTS_AUTOAGE,
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ANA_ANEVENTS_VS2TTL1,
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ANA_ANEVENTS_STORM_DROP,
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ANA_ANEVENTS_LEARN_DROP,
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ANA_ANEVENTS_AGED_ENTRY,
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ANA_ANEVENTS_CPU_LEARN_FAILED,
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ANA_ANEVENTS_AUTO_LEARN_FAILED,
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ANA_ANEVENTS_LEARN_REMOVE,
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ANA_ANEVENTS_AUTO_LEARNED,
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ANA_ANEVENTS_AUTO_MOVED,
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ANA_ANEVENTS_DROPPED,
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ANA_ANEVENTS_CLASSIFIED_DROP,
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ANA_ANEVENTS_CLASSIFIED_COPY,
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ANA_ANEVENTS_VLAN_DISCARD,
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ANA_ANEVENTS_FWD_DISCARD,
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ANA_ANEVENTS_MULTICAST_FLOOD,
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ANA_ANEVENTS_UNICAST_FLOOD,
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ANA_ANEVENTS_DEST_KNOWN,
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ANA_ANEVENTS_BUCKET3_MATCH,
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ANA_ANEVENTS_BUCKET2_MATCH,
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ANA_ANEVENTS_BUCKET1_MATCH,
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ANA_ANEVENTS_BUCKET0_MATCH,
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ANA_ANEVENTS_CPU_OPERATION,
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ANA_ANEVENTS_DMAC_LOOKUP,
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ANA_ANEVENTS_SMAC_LOOKUP,
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ANA_ANEVENTS_SEQ_GEN_ERR_0,
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ANA_ANEVENTS_SEQ_GEN_ERR_1,
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ANA_TABLES_MACACCESS_B_DOM,
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ANA_TABLES_MACTINDX_BUCKET,
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ANA_TABLES_MACTINDX_M_INDEX,
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QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
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QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
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QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
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QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
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QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
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SYS_RESET_CFG_CORE_ENA,
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SYS_RESET_CFG_MEM_ENA,
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SYS_RESET_CFG_MEM_INIT,
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GCB_SOFT_RST_SWC_RST,
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REGFIELD_MAX
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};
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enum ocelot_clk_pins {
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ALT_PPS_PIN = 1,
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EXT_CLK_PIN,
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ALT_LDST_PIN,
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TOD_ACC_PIN
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};
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struct ocelot_stat_layout {
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u32 offset;
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char name[ETH_GSTRING_LEN];
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};
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enum ocelot_tag_prefix {
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OCELOT_TAG_PREFIX_DISABLED = 0,
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OCELOT_TAG_PREFIX_NONE,
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OCELOT_TAG_PREFIX_SHORT,
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OCELOT_TAG_PREFIX_LONG,
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};
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struct ocelot;
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struct ocelot_ops {
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void (*pcs_init)(struct ocelot *ocelot, int port);
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int (*reset)(struct ocelot *ocelot);
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};
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struct ocelot_port {
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struct ocelot *ocelot;
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void __iomem *regs;
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/* Ingress default VLAN (pvid) */
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u16 pvid;
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/* Egress default VLAN (vid) */
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u16 vid;
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u8 ptp_cmd;
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struct sk_buff_head tx_skbs;
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u8 ts_id;
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phy_interface_t phy_mode;
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};
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struct ocelot {
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struct device *dev;
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const struct ocelot_ops *ops;
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struct regmap *targets[TARGET_MAX];
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struct regmap_field *regfields[REGFIELD_MAX];
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const u32 *const *map;
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const struct ocelot_stat_layout *stats_layout;
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unsigned int num_stats;
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int shared_queue_sz;
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struct net_device *hw_bridge_dev;
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u16 bridge_mask;
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u16 bridge_fwd_mask;
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struct ocelot_port **ports;
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u8 base_mac[ETH_ALEN];
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/* Keep track of the vlan port masks */
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u32 vlan_mask[VLAN_N_VID];
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u8 num_phys_ports;
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u8 num_cpu_ports;
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u8 cpu;
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u32 *lags;
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struct list_head multicast;
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/* Workqueue to check statistics for overflow with its lock */
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struct mutex stats_lock;
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u64 *stats;
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struct delayed_work stats_work;
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struct workqueue_struct *stats_queue;
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u8 ptp:1;
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struct ptp_clock *ptp_clock;
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struct ptp_clock_info ptp_info;
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struct hwtstamp_config hwtstamp_config;
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/* Protects the PTP interface state */
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struct mutex ptp_lock;
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/* Protects the PTP clock */
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spinlock_t ptp_clock_lock;
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void (*port_pcs_init)(struct ocelot_port *port);
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};
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#define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
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#define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
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#define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
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#define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
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#define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
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#define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
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#define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
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#define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
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#define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
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#define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
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#define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
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#define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
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/* I/O */
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u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
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void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
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u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
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void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
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void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
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u32 offset);
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/* Hardware initialization */
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int ocelot_regfields_init(struct ocelot *ocelot,
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const struct reg_field *const regfields);
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struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
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void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
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enum ocelot_tag_prefix injection,
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enum ocelot_tag_prefix extraction);
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int ocelot_init(struct ocelot *ocelot);
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void ocelot_deinit(struct ocelot *ocelot);
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void ocelot_init_port(struct ocelot *ocelot, int port);
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/* DSA callbacks */
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void ocelot_port_enable(struct ocelot *ocelot, int port,
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struct phy_device *phy);
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void ocelot_port_disable(struct ocelot *ocelot, int port);
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void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
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void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
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int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
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int ocelot_get_ts_info(struct ocelot *ocelot, int port,
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struct ethtool_ts_info *info);
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void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
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void ocelot_adjust_link(struct ocelot *ocelot, int port,
|
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struct phy_device *phydev);
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void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
|
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bool vlan_aware);
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void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
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int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
|
|
struct net_device *bridge);
|
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int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
|
|
struct net_device *bridge);
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int ocelot_fdb_dump(struct ocelot *ocelot, int port,
|
|
dsa_fdb_dump_cb_t *cb, void *data);
|
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int ocelot_fdb_add(struct ocelot *ocelot, int port,
|
|
const unsigned char *addr, u16 vid, bool vlan_aware);
|
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int ocelot_fdb_del(struct ocelot *ocelot, int port,
|
|
const unsigned char *addr, u16 vid);
|
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int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
|
|
bool untagged);
|
|
int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
|
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int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr);
|
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int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr);
|
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int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts);
|
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int ocelot_port_add_txtstamp_skb(struct ocelot_port *ocelot_port,
|
|
struct sk_buff *skb);
|
|
void ocelot_get_txtstamp(struct ocelot *ocelot);
|
|
|
|
#endif
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