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![Harvey Hunt](/assets/img/avatar_default.png)
Emails will bounce from my imgtec address, so update it to a new one. Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com> Cc: Harvey Hunt <harveyhuntnexus@gmail.com> Cc: linux-mtd@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
380 lines
9.6 KiB
C
380 lines
9.6 KiB
C
/*
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* JZ4780 BCH controller
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*
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* Copyright (c) 2015 Imagination Technologies
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* Author: Alex Smith <alex.smith@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include "jz4780_bch.h"
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#define BCH_BHCR 0x0
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#define BCH_BHCCR 0x8
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#define BCH_BHCNT 0xc
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#define BCH_BHDR 0x10
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#define BCH_BHPAR0 0x14
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#define BCH_BHERR0 0x84
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#define BCH_BHINT 0x184
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#define BCH_BHINTES 0x188
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#define BCH_BHINTEC 0x18c
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#define BCH_BHINTE 0x190
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#define BCH_BHCR_BSEL_SHIFT 4
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#define BCH_BHCR_BSEL_MASK (0x7f << BCH_BHCR_BSEL_SHIFT)
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#define BCH_BHCR_ENCE BIT(2)
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#define BCH_BHCR_INIT BIT(1)
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#define BCH_BHCR_BCHE BIT(0)
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#define BCH_BHCNT_PARITYSIZE_SHIFT 16
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#define BCH_BHCNT_PARITYSIZE_MASK (0x7f << BCH_BHCNT_PARITYSIZE_SHIFT)
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#define BCH_BHCNT_BLOCKSIZE_SHIFT 0
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#define BCH_BHCNT_BLOCKSIZE_MASK (0x7ff << BCH_BHCNT_BLOCKSIZE_SHIFT)
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#define BCH_BHERR_MASK_SHIFT 16
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#define BCH_BHERR_MASK_MASK (0xffff << BCH_BHERR_MASK_SHIFT)
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#define BCH_BHERR_INDEX_SHIFT 0
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#define BCH_BHERR_INDEX_MASK (0x7ff << BCH_BHERR_INDEX_SHIFT)
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#define BCH_BHINT_ERRC_SHIFT 24
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#define BCH_BHINT_ERRC_MASK (0x7f << BCH_BHINT_ERRC_SHIFT)
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#define BCH_BHINT_TERRC_SHIFT 16
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#define BCH_BHINT_TERRC_MASK (0x7f << BCH_BHINT_TERRC_SHIFT)
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#define BCH_BHINT_DECF BIT(3)
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#define BCH_BHINT_ENCF BIT(2)
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#define BCH_BHINT_UNCOR BIT(1)
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#define BCH_BHINT_ERR BIT(0)
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#define BCH_CLK_RATE (200 * 1000 * 1000)
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/* Timeout for BCH calculation/correction. */
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#define BCH_TIMEOUT_US 100000
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struct jz4780_bch {
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struct device *dev;
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void __iomem *base;
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struct clk *clk;
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struct mutex lock;
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};
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static void jz4780_bch_init(struct jz4780_bch *bch,
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struct jz4780_bch_params *params, bool encode)
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{
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u32 reg;
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/* Clear interrupt status. */
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writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);
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/* Set up BCH count register. */
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reg = params->size << BCH_BHCNT_BLOCKSIZE_SHIFT;
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reg |= params->bytes << BCH_BHCNT_PARITYSIZE_SHIFT;
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writel(reg, bch->base + BCH_BHCNT);
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/* Initialise and enable BCH. */
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reg = BCH_BHCR_BCHE | BCH_BHCR_INIT;
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reg |= params->strength << BCH_BHCR_BSEL_SHIFT;
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if (encode)
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reg |= BCH_BHCR_ENCE;
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writel(reg, bch->base + BCH_BHCR);
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}
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static void jz4780_bch_disable(struct jz4780_bch *bch)
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{
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writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);
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writel(BCH_BHCR_BCHE, bch->base + BCH_BHCCR);
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}
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static void jz4780_bch_write_data(struct jz4780_bch *bch, const void *buf,
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size_t size)
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{
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size_t size32 = size / sizeof(u32);
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size_t size8 = size % sizeof(u32);
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const u32 *src32;
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const u8 *src8;
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src32 = (const u32 *)buf;
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while (size32--)
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writel(*src32++, bch->base + BCH_BHDR);
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src8 = (const u8 *)src32;
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while (size8--)
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writeb(*src8++, bch->base + BCH_BHDR);
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}
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static void jz4780_bch_read_parity(struct jz4780_bch *bch, void *buf,
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size_t size)
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{
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size_t size32 = size / sizeof(u32);
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size_t size8 = size % sizeof(u32);
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u32 *dest32;
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u8 *dest8;
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u32 val, offset = 0;
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dest32 = (u32 *)buf;
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while (size32--) {
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*dest32++ = readl(bch->base + BCH_BHPAR0 + offset);
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offset += sizeof(u32);
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}
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dest8 = (u8 *)dest32;
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val = readl(bch->base + BCH_BHPAR0 + offset);
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switch (size8) {
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case 3:
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dest8[2] = (val >> 16) & 0xff;
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case 2:
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dest8[1] = (val >> 8) & 0xff;
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case 1:
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dest8[0] = val & 0xff;
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break;
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}
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}
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static bool jz4780_bch_wait_complete(struct jz4780_bch *bch, unsigned int irq,
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u32 *status)
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{
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u32 reg;
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int ret;
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/*
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* While we could use interrupts here and sleep until the operation
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* completes, the controller works fairly quickly (usually a few
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* microseconds) and so the overhead of sleeping until we get an
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* interrupt quite noticeably decreases performance.
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*/
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ret = readl_poll_timeout(bch->base + BCH_BHINT, reg,
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(reg & irq) == irq, 0, BCH_TIMEOUT_US);
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if (ret)
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return false;
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if (status)
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*status = reg;
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writel(reg, bch->base + BCH_BHINT);
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return true;
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}
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/**
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* jz4780_bch_calculate() - calculate ECC for a data buffer
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* @bch: BCH device.
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* @params: BCH parameters.
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* @buf: input buffer with raw data.
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* @ecc_code: output buffer with ECC.
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*
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* Return: 0 on success, -ETIMEDOUT if timed out while waiting for BCH
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* controller.
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*/
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int jz4780_bch_calculate(struct jz4780_bch *bch, struct jz4780_bch_params *params,
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const u8 *buf, u8 *ecc_code)
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{
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int ret = 0;
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mutex_lock(&bch->lock);
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jz4780_bch_init(bch, params, true);
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jz4780_bch_write_data(bch, buf, params->size);
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if (jz4780_bch_wait_complete(bch, BCH_BHINT_ENCF, NULL)) {
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jz4780_bch_read_parity(bch, ecc_code, params->bytes);
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} else {
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dev_err(bch->dev, "timed out while calculating ECC\n");
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ret = -ETIMEDOUT;
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}
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jz4780_bch_disable(bch);
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mutex_unlock(&bch->lock);
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return ret;
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}
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EXPORT_SYMBOL(jz4780_bch_calculate);
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/**
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* jz4780_bch_correct() - detect and correct bit errors
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* @bch: BCH device.
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* @params: BCH parameters.
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* @buf: raw data read from the chip.
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* @ecc_code: ECC read from the chip.
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*
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* Given the raw data and the ECC read from the NAND device, detects and
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* corrects errors in the data.
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*
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* Return: the number of bit errors corrected, -EBADMSG if there are too many
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* errors to correct or -ETIMEDOUT if we timed out waiting for the controller.
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*/
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int jz4780_bch_correct(struct jz4780_bch *bch, struct jz4780_bch_params *params,
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u8 *buf, u8 *ecc_code)
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{
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u32 reg, mask, index;
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int i, ret, count;
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mutex_lock(&bch->lock);
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jz4780_bch_init(bch, params, false);
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jz4780_bch_write_data(bch, buf, params->size);
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jz4780_bch_write_data(bch, ecc_code, params->bytes);
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if (!jz4780_bch_wait_complete(bch, BCH_BHINT_DECF, ®)) {
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dev_err(bch->dev, "timed out while correcting data\n");
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ret = -ETIMEDOUT;
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goto out;
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}
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if (reg & BCH_BHINT_UNCOR) {
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dev_warn(bch->dev, "uncorrectable ECC error\n");
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ret = -EBADMSG;
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goto out;
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}
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/* Correct any detected errors. */
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if (reg & BCH_BHINT_ERR) {
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count = (reg & BCH_BHINT_ERRC_MASK) >> BCH_BHINT_ERRC_SHIFT;
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ret = (reg & BCH_BHINT_TERRC_MASK) >> BCH_BHINT_TERRC_SHIFT;
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for (i = 0; i < count; i++) {
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reg = readl(bch->base + BCH_BHERR0 + (i * 4));
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mask = (reg & BCH_BHERR_MASK_MASK) >>
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BCH_BHERR_MASK_SHIFT;
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index = (reg & BCH_BHERR_INDEX_MASK) >>
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BCH_BHERR_INDEX_SHIFT;
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buf[(index * 2) + 0] ^= mask;
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buf[(index * 2) + 1] ^= mask >> 8;
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}
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} else {
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ret = 0;
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}
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out:
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jz4780_bch_disable(bch);
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mutex_unlock(&bch->lock);
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return ret;
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}
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EXPORT_SYMBOL(jz4780_bch_correct);
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/**
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* jz4780_bch_get() - get the BCH controller device
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* @np: BCH device tree node.
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*
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* Gets the BCH controller device from the specified device tree node. The
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* device must be released with jz4780_bch_release() when it is no longer being
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* used.
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*
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* Return: a pointer to jz4780_bch, errors are encoded into the pointer.
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* PTR_ERR(-EPROBE_DEFER) if the device hasn't been initialised yet.
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*/
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static struct jz4780_bch *jz4780_bch_get(struct device_node *np)
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{
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struct platform_device *pdev;
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struct jz4780_bch *bch;
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pdev = of_find_device_by_node(np);
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if (!pdev || !platform_get_drvdata(pdev))
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return ERR_PTR(-EPROBE_DEFER);
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get_device(&pdev->dev);
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bch = platform_get_drvdata(pdev);
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clk_prepare_enable(bch->clk);
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return bch;
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}
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/**
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* of_jz4780_bch_get() - get the BCH controller from a DT node
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* @of_node: the node that contains a bch-controller property.
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*
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* Get the bch-controller property from the given device tree
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* node and pass it to jz4780_bch_get to do the work.
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*
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* Return: a pointer to jz4780_bch, errors are encoded into the pointer.
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* PTR_ERR(-EPROBE_DEFER) if the device hasn't been initialised yet.
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*/
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struct jz4780_bch *of_jz4780_bch_get(struct device_node *of_node)
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{
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struct jz4780_bch *bch = NULL;
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struct device_node *np;
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np = of_parse_phandle(of_node, "ingenic,bch-controller", 0);
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if (np) {
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bch = jz4780_bch_get(np);
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of_node_put(np);
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}
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return bch;
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}
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EXPORT_SYMBOL(of_jz4780_bch_get);
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/**
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* jz4780_bch_release() - release the BCH controller device
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* @bch: BCH device.
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*/
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void jz4780_bch_release(struct jz4780_bch *bch)
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{
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clk_disable_unprepare(bch->clk);
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put_device(bch->dev);
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}
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EXPORT_SYMBOL(jz4780_bch_release);
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static int jz4780_bch_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct jz4780_bch *bch;
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struct resource *res;
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bch = devm_kzalloc(dev, sizeof(*bch), GFP_KERNEL);
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if (!bch)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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bch->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(bch->base))
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return PTR_ERR(bch->base);
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jz4780_bch_disable(bch);
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bch->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(bch->clk)) {
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dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(bch->clk));
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return PTR_ERR(bch->clk);
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}
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clk_set_rate(bch->clk, BCH_CLK_RATE);
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mutex_init(&bch->lock);
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bch->dev = dev;
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platform_set_drvdata(pdev, bch);
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return 0;
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}
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static const struct of_device_id jz4780_bch_dt_match[] = {
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{ .compatible = "ingenic,jz4780-bch" },
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{},
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};
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MODULE_DEVICE_TABLE(of, jz4780_bch_dt_match);
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static struct platform_driver jz4780_bch_driver = {
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.probe = jz4780_bch_probe,
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.driver = {
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.name = "jz4780-bch",
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.of_match_table = of_match_ptr(jz4780_bch_dt_match),
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},
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};
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module_platform_driver(jz4780_bch_driver);
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MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
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MODULE_AUTHOR("Harvey Hunt <harveyhuntnexus@gmail.com>");
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MODULE_DESCRIPTION("Ingenic JZ4780 BCH error correction driver");
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MODULE_LICENSE("GPL v2");
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