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![Jani Nikula](/assets/img/avatar_default.png)
Everything about the file is about display, and mostly about types related to display. Move under display/ as intel_display_types.h to reflect the facts. There's still plenty to clean up, but start off with moving the file where it logically belongs and naming according to contents. v2: fix the include guard name in the renamed file Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190806113933.11799-1-jani.nikula@intel.com
391 lines
10 KiB
C
391 lines
10 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2018 Intel Corporation
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*/
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#include "intel_combo_phy.h"
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#include "intel_display_types.h"
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#define for_each_combo_phy(__dev_priv, __phy) \
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for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
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for_each_if(intel_phy_is_combo(__dev_priv, __phy))
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#define for_each_combo_phy_reverse(__dev_priv, __phy) \
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for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
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for_each_if(intel_phy_is_combo(__dev_priv, __phy))
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enum {
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PROCMON_0_85V_DOT_0,
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PROCMON_0_95V_DOT_0,
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PROCMON_0_95V_DOT_1,
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PROCMON_1_05V_DOT_0,
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PROCMON_1_05V_DOT_1,
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};
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static const struct cnl_procmon {
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u32 dw1, dw9, dw10;
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} cnl_procmon_values[] = {
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[PROCMON_0_85V_DOT_0] =
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{ .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
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[PROCMON_0_95V_DOT_0] =
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{ .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
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[PROCMON_0_95V_DOT_1] =
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{ .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
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[PROCMON_1_05V_DOT_0] =
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{ .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
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[PROCMON_1_05V_DOT_1] =
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{ .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
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};
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/*
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* CNL has just one set of registers, while gen11 has a set for each combo PHY.
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* The CNL registers are equivalent to the gen11 PHY A registers, that's why we
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* call the ICL macros even though the function has CNL on its name.
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*/
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static const struct cnl_procmon *
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cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
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{
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const struct cnl_procmon *procmon;
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u32 val;
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val = I915_READ(ICL_PORT_COMP_DW3(phy));
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switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
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default:
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MISSING_CASE(val);
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/* fall through */
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case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
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procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
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break;
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case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
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procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
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break;
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case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
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procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
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break;
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case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
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procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
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break;
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case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
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procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
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break;
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}
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return procmon;
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}
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static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
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enum phy phy)
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{
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const struct cnl_procmon *procmon;
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u32 val;
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procmon = cnl_get_procmon_ref_values(dev_priv, phy);
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val = I915_READ(ICL_PORT_COMP_DW1(phy));
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val &= ~((0xff << 16) | 0xff);
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val |= procmon->dw1;
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I915_WRITE(ICL_PORT_COMP_DW1(phy), val);
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I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9);
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I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10);
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}
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static bool check_phy_reg(struct drm_i915_private *dev_priv,
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enum phy phy, i915_reg_t reg, u32 mask,
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u32 expected_val)
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{
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u32 val = I915_READ(reg);
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if ((val & mask) != expected_val) {
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DRM_DEBUG_DRIVER("Combo PHY %c reg %08x state mismatch: "
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"current %08x mask %08x expected %08x\n",
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phy_name(phy),
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reg.reg, val, mask, expected_val);
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return false;
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}
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return true;
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}
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static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
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enum phy phy)
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{
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const struct cnl_procmon *procmon;
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bool ret;
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procmon = cnl_get_procmon_ref_values(dev_priv, phy);
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ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
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(0xff << 16) | 0xff, procmon->dw1);
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ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
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-1U, procmon->dw9);
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ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),
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-1U, procmon->dw10);
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return ret;
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}
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static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv)
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{
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return !(I915_READ(CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) &&
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(I915_READ(CNL_PORT_COMP_DW0) & COMP_INIT);
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}
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static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv)
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{
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enum phy phy = PHY_A;
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bool ret;
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if (!cnl_combo_phy_enabled(dev_priv))
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return false;
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ret = cnl_verify_procmon_ref_values(dev_priv, phy);
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ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,
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CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
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return ret;
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}
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static void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
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{
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u32 val;
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val = I915_READ(CHICKEN_MISC_2);
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val &= ~CNL_COMP_PWR_DOWN;
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I915_WRITE(CHICKEN_MISC_2, val);
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/* Dummy PORT_A to get the correct CNL register from the ICL macro */
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cnl_set_procmon_ref_values(dev_priv, PHY_A);
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val = I915_READ(CNL_PORT_COMP_DW0);
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val |= COMP_INIT;
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I915_WRITE(CNL_PORT_COMP_DW0, val);
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val = I915_READ(CNL_PORT_CL1CM_DW5);
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val |= CL_POWER_DOWN_ENABLE;
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I915_WRITE(CNL_PORT_CL1CM_DW5, val);
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}
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static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
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{
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u32 val;
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if (!cnl_combo_phy_verify_state(dev_priv))
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DRM_WARN("Combo PHY HW state changed unexpectedly.\n");
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val = I915_READ(CHICKEN_MISC_2);
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val |= CNL_COMP_PWR_DOWN;
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I915_WRITE(CHICKEN_MISC_2, val);
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}
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static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
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enum phy phy)
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{
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/* The PHY C added by EHL has no PHY_MISC register */
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if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
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return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
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else
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return !(I915_READ(ICL_PHY_MISC(phy)) &
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ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
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(I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
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}
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static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
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enum phy phy)
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{
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bool ret;
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if (!icl_combo_phy_enabled(dev_priv, phy))
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return false;
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ret = cnl_verify_procmon_ref_values(dev_priv, phy);
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if (phy == PHY_A)
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ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
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IREFGEN, IREFGEN);
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ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
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CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
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return ret;
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}
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void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
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enum phy phy, bool is_dsi,
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int lane_count, bool lane_reversal)
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{
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u8 lane_mask;
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u32 val;
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if (is_dsi) {
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WARN_ON(lane_reversal);
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switch (lane_count) {
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case 1:
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lane_mask = PWR_DOWN_LN_3_1_0;
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break;
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case 2:
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lane_mask = PWR_DOWN_LN_3_1;
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break;
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case 3:
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lane_mask = PWR_DOWN_LN_3;
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break;
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default:
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MISSING_CASE(lane_count);
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/* fall-through */
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case 4:
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lane_mask = PWR_UP_ALL_LANES;
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break;
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}
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} else {
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switch (lane_count) {
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case 1:
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lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 :
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PWR_DOWN_LN_3_2_1;
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break;
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case 2:
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lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 :
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PWR_DOWN_LN_3_2;
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break;
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default:
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MISSING_CASE(lane_count);
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/* fall-through */
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case 4:
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lane_mask = PWR_UP_ALL_LANES;
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break;
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}
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}
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val = I915_READ(ICL_PORT_CL_DW10(phy));
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val &= ~PWR_DOWN_LN_MASK;
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val |= lane_mask << PWR_DOWN_LN_SHIFT;
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I915_WRITE(ICL_PORT_CL_DW10(phy), val);
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}
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static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val)
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{
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bool ddi_a_present = i915->vbt.ddi_port_info[PORT_A].child != NULL;
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bool ddi_d_present = i915->vbt.ddi_port_info[PORT_D].child != NULL;
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bool dsi_present = intel_bios_is_dsi_present(i915, NULL);
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/*
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* VBT's 'dvo port' field for child devices references the DDI, not
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* the PHY. So if combo PHY A is wired up to drive an external
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* display, we should see a child device present on PORT_D and
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* nothing on PORT_A and no DSI.
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*/
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if (ddi_d_present && !ddi_a_present && !dsi_present)
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return val | ICL_PHY_MISC_MUX_DDID;
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/*
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* If we encounter a VBT that claims to have an external display on
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* DDI-D _and_ an internal display on DDI-A/DSI leave an error message
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* in the log and let the internal display win.
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*/
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if (ddi_d_present)
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DRM_ERROR("VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n");
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return val & ~ICL_PHY_MISC_MUX_DDID;
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}
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static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
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{
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enum phy phy;
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for_each_combo_phy(dev_priv, phy) {
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u32 val;
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if (icl_combo_phy_verify_state(dev_priv, phy)) {
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DRM_DEBUG_DRIVER("Combo PHY %c already enabled, won't reprogram it.\n",
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phy_name(phy));
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continue;
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}
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/*
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* Although EHL adds a combo PHY C, there's no PHY_MISC
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* register for it and no need to program the
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* DE_IO_COMP_PWR_DOWN setting on PHY C.
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*/
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if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
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goto skip_phy_misc;
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/*
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* EHL's combo PHY A can be hooked up to either an external
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* display (via DDI-D) or an internal display (via DDI-A or
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* the DSI DPHY). This is a motherboard design decision that
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* can't be changed on the fly, so initialize the PHY's mux
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* based on whether our VBT indicates the presence of any
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* "internal" child devices.
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*/
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val = I915_READ(ICL_PHY_MISC(phy));
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if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A)
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val = ehl_combo_phy_a_mux(dev_priv, val);
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val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
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I915_WRITE(ICL_PHY_MISC(phy), val);
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skip_phy_misc:
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cnl_set_procmon_ref_values(dev_priv, phy);
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if (phy == PHY_A) {
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val = I915_READ(ICL_PORT_COMP_DW8(phy));
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val |= IREFGEN;
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I915_WRITE(ICL_PORT_COMP_DW8(phy), val);
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}
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val = I915_READ(ICL_PORT_COMP_DW0(phy));
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val |= COMP_INIT;
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I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
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val = I915_READ(ICL_PORT_CL_DW5(phy));
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val |= CL_POWER_DOWN_ENABLE;
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I915_WRITE(ICL_PORT_CL_DW5(phy), val);
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}
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}
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static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
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{
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enum phy phy;
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for_each_combo_phy_reverse(dev_priv, phy) {
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u32 val;
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if (phy == PHY_A &&
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!icl_combo_phy_verify_state(dev_priv, phy))
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DRM_WARN("Combo PHY %c HW state changed unexpectedly\n",
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phy_name(phy));
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/*
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* Although EHL adds a combo PHY C, there's no PHY_MISC
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* register for it and no need to program the
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* DE_IO_COMP_PWR_DOWN setting on PHY C.
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*/
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if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
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goto skip_phy_misc;
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val = I915_READ(ICL_PHY_MISC(phy));
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val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
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I915_WRITE(ICL_PHY_MISC(phy), val);
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skip_phy_misc:
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val = I915_READ(ICL_PORT_COMP_DW0(phy));
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val &= ~COMP_INIT;
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I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
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}
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}
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void intel_combo_phy_init(struct drm_i915_private *i915)
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{
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if (INTEL_GEN(i915) >= 11)
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icl_combo_phys_init(i915);
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else if (IS_CANNONLAKE(i915))
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cnl_combo_phys_init(i915);
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}
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void intel_combo_phy_uninit(struct drm_i915_private *i915)
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{
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if (INTEL_GEN(i915) >= 11)
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icl_combo_phys_uninit(i915);
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else if (IS_CANNONLAKE(i915))
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cnl_combo_phys_uninit(i915);
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}
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