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0c06fa1560
When BT.2020 Colorimetry output is used for DP, we should program BT.2020
Colorimetry to MSA and VSC SDP. In order to handle colorspace of
drm_connector_state, it moves a calling of intel_ddi_set_pipe_settings()
function into intel_ddi_pre_enable_dp(). And it also rename
intel_ddi_set_pipe_settings() to intel_ddi_set_dp_msa().
As per DP 1.4a spec section 2.2.4 [MSA Data Transport]
The MSA data that the DP Source device transports for reproducing the main
video stream. Attribute data is sent once per frame during the main video
stream’s vertical blanking period.
In order to distinguish needed colorimetry for VSC SDP, it adds
intel_dp_needs_vsc_sdp function.
If the output colorspace requires vsc sdp or output format is YCbCr 4:2:0,
it uses MSA with VSC SDP.
As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication of
Color Encoding Format and Content Color Gamut] while sending
BT.2020 Colorimetry signals we should program MSA MISC1 fields which
indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
v2: Remove useless parentheses
v3: Addressed review comments from Ville
- In order to checking output format and output colorspace on
intel_dp_needs_vsc_sdp(), it passes entire intel_crtc_state struct
value.
- Remove a pointless variable.
v9: Addressed review comments from Ville
- Remove a duplicated output color space from intel_crtc_state.
- In order to handle colorspace of drm_connector_state, it moves a
calling of intel_ddi_set_pipe_settings() function into
intel_ddi_pre_enable_dp().
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190919195311.13972-3-gwan-gyeong.mun@intel.com
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
53 lines
2.1 KiB
C
53 lines
2.1 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DDI_H__
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#define __INTEL_DDI_H__
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#include <drm/i915_drm.h>
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#include "intel_display.h"
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struct drm_connector_state;
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struct drm_i915_private;
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struct intel_connector;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_dp;
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struct intel_dpll_hw_state;
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struct intel_encoder;
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void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
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const struct intel_crtc_state *old_crtc_state,
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const struct drm_connector_state *old_conn_state);
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void hsw_fdi_link_train(struct intel_crtc *crtc,
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const struct intel_crtc_state *crtc_state);
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void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
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bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
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void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
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void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
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void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
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void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
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void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state);
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bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
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void intel_ddi_get_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config);
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void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
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bool state);
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void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
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struct intel_crtc_state *crtc_state);
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u32 bxt_signal_levels(struct intel_dp *intel_dp);
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u32 ddi_signal_levels(struct intel_dp *intel_dp);
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u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
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u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
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u8 voltage_swing);
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int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
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bool enable);
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void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
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int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
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struct intel_dpll_hw_state *state);
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#endif /* __INTEL_DDI_H__ */
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