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df0566a641
Now that we have a new subdirectory for display code, continue by moving modesetting core code. display/intel_frontbuffer.h sticks out like a sore thumb, otherwise this is, again, a surprisingly clean operation. v2: - don't move intel_sideband.[ch] (Ville) - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-3-jani.nikula@intel.com
58 lines
2.3 KiB
C
58 lines
2.3 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DPIO_PHY_H__
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#define __INTEL_DPIO_PHY_H__
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#include <linux/types.h>
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enum dpio_channel;
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enum dpio_phy;
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enum port;
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struct drm_i915_private;
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struct intel_crtc_state;
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struct intel_encoder;
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void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
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enum dpio_phy *phy, enum dpio_channel *ch);
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void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
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enum port port, u32 margin, u32 scale,
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u32 enable, u32 deemphasis);
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void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
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void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
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bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
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enum dpio_phy phy);
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bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
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enum dpio_phy phy);
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u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count);
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void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
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u8 lane_lat_optim_mask);
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u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
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void chv_set_phy_signal_level(struct intel_encoder *encoder,
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u32 deemph_reg_value, u32 margin_reg_value,
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bool uniq_trans_scale);
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void chv_data_lane_soft_reset(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state,
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bool reset);
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void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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void chv_phy_release_cl2_override(struct intel_encoder *encoder);
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void chv_phy_post_pll_disable(struct intel_encoder *encoder,
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const struct intel_crtc_state *old_crtc_state);
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void vlv_set_phy_signal_level(struct intel_encoder *encoder,
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u32 demph_reg_value, u32 preemph_reg_value,
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u32 uniqtranscale_reg_value, u32 tx3_demph);
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void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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void vlv_phy_reset_lanes(struct intel_encoder *encoder,
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const struct intel_crtc_state *old_crtc_state);
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#endif /* __INTEL_DPIO_PHY_H__ */
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