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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
![Maarten Lankhorst](/assets/img/avatar_default.png)
We are still looking at drm_crtc_state in a few places, convert those to use intel_crtc_state instead. Changes since v1: - Move to before uapi/hw split. - Add hunks for intel_pm.c as well. Changes since v2: - Incorporate Ville's feedback. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191031112610.27608-1-maarten.lankhorst@linux.intel.com
1446 lines
42 KiB
C
1446 lines
42 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <drm/drm_atomic_helper.h>
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#include "display/intel_dp.h"
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#include "i915_drv.h"
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#include "intel_atomic.h"
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#include "intel_display_types.h"
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#include "intel_psr.h"
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#include "intel_sprite.h"
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/**
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* DOC: Panel Self Refresh (PSR/SRD)
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*
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* Since Haswell Display controller supports Panel Self-Refresh on display
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* panels witch have a remote frame buffer (RFB) implemented according to PSR
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* spec in eDP1.3. PSR feature allows the display to go to lower standby states
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* when system is idle but display is on as it eliminates display refresh
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* request to DDR memory completely as long as the frame buffer for that
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* display is unchanged.
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*
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* Panel Self Refresh must be supported by both Hardware (source) and
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* Panel (sink).
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*
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* PSR saves power by caching the framebuffer in the panel RFB, which allows us
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* to power down the link and memory controller. For DSI panels the same idea
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* is called "manual mode".
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*
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* The implementation uses the hardware-based PSR support which automatically
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* enters/exits self-refresh mode. The hardware takes care of sending the
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* required DP aux message and could even retrain the link (that part isn't
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* enabled yet though). The hardware also keeps track of any frontbuffer
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* changes to know when to exit self-refresh mode again. Unfortunately that
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* part doesn't work too well, hence why the i915 PSR support uses the
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* software frontbuffer tracking to make sure it doesn't miss a screen
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* update. For this integration intel_psr_invalidate() and intel_psr_flush()
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* get called by the frontbuffer tracking code. Note that because of locking
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* issues the self-refresh re-enable code is done from a work queue, which
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* must be correctly synchronized/cancelled when shutting down the pipe."
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*/
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static bool psr_global_enabled(u32 debug)
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{
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switch (debug & I915_PSR_DEBUG_MODE_MASK) {
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case I915_PSR_DEBUG_DEFAULT:
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return i915_modparams.enable_psr;
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case I915_PSR_DEBUG_DISABLE:
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return false;
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default:
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return true;
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}
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}
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static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
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const struct intel_crtc_state *crtc_state)
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{
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/* Cannot enable DSC and PSR2 simultaneously */
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WARN_ON(crtc_state->dsc.compression_enable &&
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crtc_state->has_psr2);
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switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
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case I915_PSR_DEBUG_DISABLE:
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case I915_PSR_DEBUG_FORCE_PSR1:
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return false;
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default:
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return crtc_state->has_psr2;
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}
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}
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static void psr_irq_control(struct drm_i915_private *dev_priv)
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{
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enum transcoder trans_shift;
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u32 mask, val;
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i915_reg_t imr_reg;
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/*
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* gen12+ has registers relative to transcoder and one per transcoder
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* using the same bit definition: handle it as TRANSCODER_EDP to force
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* 0 shift in bit definition
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*/
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if (INTEL_GEN(dev_priv) >= 12) {
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trans_shift = 0;
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imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder);
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} else {
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trans_shift = dev_priv->psr.transcoder;
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imr_reg = EDP_PSR_IMR;
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}
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mask = EDP_PSR_ERROR(trans_shift);
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if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
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mask |= EDP_PSR_POST_EXIT(trans_shift) |
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EDP_PSR_PRE_ENTRY(trans_shift);
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/* Warning: it is masking/setting reserved bits too */
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val = I915_READ(imr_reg);
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val &= ~EDP_PSR_TRANS_MASK(trans_shift);
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val |= ~mask;
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I915_WRITE(imr_reg, val);
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}
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static void psr_event_print(u32 val, bool psr2_enabled)
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{
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DRM_DEBUG_KMS("PSR exit events: 0x%x\n", val);
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if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
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DRM_DEBUG_KMS("\tPSR2 watchdog timer expired\n");
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if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
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DRM_DEBUG_KMS("\tPSR2 disabled\n");
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if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
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DRM_DEBUG_KMS("\tSU dirty FIFO underrun\n");
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if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN)
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DRM_DEBUG_KMS("\tSU CRC FIFO underrun\n");
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if (val & PSR_EVENT_GRAPHICS_RESET)
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DRM_DEBUG_KMS("\tGraphics reset\n");
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if (val & PSR_EVENT_PCH_INTERRUPT)
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DRM_DEBUG_KMS("\tPCH interrupt\n");
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if (val & PSR_EVENT_MEMORY_UP)
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DRM_DEBUG_KMS("\tMemory up\n");
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if (val & PSR_EVENT_FRONT_BUFFER_MODIFY)
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DRM_DEBUG_KMS("\tFront buffer modification\n");
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if (val & PSR_EVENT_WD_TIMER_EXPIRE)
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DRM_DEBUG_KMS("\tPSR watchdog timer expired\n");
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if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE)
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DRM_DEBUG_KMS("\tPIPE registers updated\n");
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if (val & PSR_EVENT_REGISTER_UPDATE)
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DRM_DEBUG_KMS("\tRegister updated\n");
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if (val & PSR_EVENT_HDCP_ENABLE)
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DRM_DEBUG_KMS("\tHDCP enabled\n");
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if (val & PSR_EVENT_KVMR_SESSION_ENABLE)
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DRM_DEBUG_KMS("\tKVMR session enabled\n");
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if (val & PSR_EVENT_VBI_ENABLE)
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DRM_DEBUG_KMS("\tVBI enabled\n");
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if (val & PSR_EVENT_LPSP_MODE_EXIT)
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DRM_DEBUG_KMS("\tLPSP mode exited\n");
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if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
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DRM_DEBUG_KMS("\tPSR disabled\n");
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}
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void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
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{
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enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
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enum transcoder trans_shift;
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i915_reg_t imr_reg;
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ktime_t time_ns = ktime_get();
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if (INTEL_GEN(dev_priv) >= 12) {
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trans_shift = 0;
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imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder);
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} else {
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trans_shift = dev_priv->psr.transcoder;
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imr_reg = EDP_PSR_IMR;
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}
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if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) {
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dev_priv->psr.last_entry_attempt = time_ns;
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DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
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transcoder_name(cpu_transcoder));
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}
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if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) {
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dev_priv->psr.last_exit = time_ns;
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DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
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transcoder_name(cpu_transcoder));
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if (INTEL_GEN(dev_priv) >= 9) {
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u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
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bool psr2_enabled = dev_priv->psr.psr2_enabled;
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I915_WRITE(PSR_EVENT(cpu_transcoder), val);
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psr_event_print(val, psr2_enabled);
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}
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}
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if (psr_iir & EDP_PSR_ERROR(trans_shift)) {
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u32 val;
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DRM_WARN("[transcoder %s] PSR aux error\n",
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transcoder_name(cpu_transcoder));
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dev_priv->psr.irq_aux_error = true;
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/*
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* If this interruption is not masked it will keep
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* interrupting so fast that it prevents the scheduled
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* work to run.
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* Also after a PSR error, we don't want to arm PSR
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* again so we don't care about unmask the interruption
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* or unset irq_aux_error.
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*/
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val = I915_READ(imr_reg);
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val |= EDP_PSR_ERROR(trans_shift);
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I915_WRITE(imr_reg, val);
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schedule_work(&dev_priv->psr.work);
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}
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}
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static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
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{
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u8 alpm_caps = 0;
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if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
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&alpm_caps) != 1)
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return false;
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return alpm_caps & DP_ALPM_CAP;
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}
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static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
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{
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u8 val = 8; /* assume the worst if we can't read the value */
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if (drm_dp_dpcd_readb(&intel_dp->aux,
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DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
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val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
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else
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DRM_DEBUG_KMS("Unable to get sink synchronization latency, assuming 8 frames\n");
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return val;
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}
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static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp)
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{
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u16 val;
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ssize_t r;
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/*
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* Returning the default X granularity if granularity not required or
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* if DPCD read fails
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*/
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if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED))
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return 4;
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r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2);
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if (r != 2)
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DRM_DEBUG_KMS("Unable to read DP_PSR2_SU_X_GRANULARITY\n");
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/*
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* Spec says that if the value read is 0 the default granularity should
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* be used instead.
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*/
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if (r != 2 || val == 0)
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val = 4;
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return val;
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}
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void intel_psr_init_dpcd(struct intel_dp *intel_dp)
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{
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struct drm_i915_private *dev_priv =
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to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
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if (dev_priv->psr.dp) {
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DRM_WARN("More than one eDP panel found, PSR support should be extended\n");
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return;
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}
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drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
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sizeof(intel_dp->psr_dpcd));
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if (!intel_dp->psr_dpcd[0])
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return;
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DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
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intel_dp->psr_dpcd[0]);
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if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
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DRM_DEBUG_KMS("PSR support not currently available for this panel\n");
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return;
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}
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if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
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DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n");
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return;
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}
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dev_priv->psr.sink_support = true;
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dev_priv->psr.sink_sync_latency =
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intel_dp_get_sink_sync_latency(intel_dp);
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dev_priv->psr.dp = intel_dp;
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if (INTEL_GEN(dev_priv) >= 9 &&
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(intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
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bool y_req = intel_dp->psr_dpcd[1] &
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DP_PSR2_SU_Y_COORDINATE_REQUIRED;
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bool alpm = intel_dp_get_alpm_status(intel_dp);
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/*
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* All panels that supports PSR version 03h (PSR2 +
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* Y-coordinate) can handle Y-coordinates in VSC but we are
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* only sure that it is going to be used when required by the
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* panel. This way panel is capable to do selective update
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* without a aux frame sync.
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*
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* To support PSR version 02h and PSR version 03h without
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* Y-coordinate requirement panels we would need to enable
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* GTC first.
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*/
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dev_priv->psr.sink_psr2_support = y_req && alpm;
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DRM_DEBUG_KMS("PSR2 %ssupported\n",
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dev_priv->psr.sink_psr2_support ? "" : "not ");
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if (dev_priv->psr.sink_psr2_support) {
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dev_priv->psr.colorimetry_support =
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intel_dp_get_colorimetry_status(intel_dp);
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dev_priv->psr.su_x_granularity =
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intel_dp_get_su_x_granulartiy(intel_dp);
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}
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}
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}
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static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state)
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{
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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struct dp_sdp psr_vsc;
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if (dev_priv->psr.psr2_enabled) {
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/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
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memset(&psr_vsc, 0, sizeof(psr_vsc));
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psr_vsc.sdp_header.HB0 = 0;
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psr_vsc.sdp_header.HB1 = 0x7;
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if (dev_priv->psr.colorimetry_support) {
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psr_vsc.sdp_header.HB2 = 0x5;
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psr_vsc.sdp_header.HB3 = 0x13;
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} else {
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psr_vsc.sdp_header.HB2 = 0x4;
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psr_vsc.sdp_header.HB3 = 0xe;
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}
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} else {
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/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
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memset(&psr_vsc, 0, sizeof(psr_vsc));
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psr_vsc.sdp_header.HB0 = 0;
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psr_vsc.sdp_header.HB1 = 0x7;
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psr_vsc.sdp_header.HB2 = 0x2;
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psr_vsc.sdp_header.HB3 = 0x8;
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}
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intel_dig_port->write_infoframe(&intel_dig_port->base,
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crtc_state,
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DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
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}
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static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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u32 aux_clock_divider, aux_ctl;
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int i;
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static const u8 aux_msg[] = {
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[0] = DP_AUX_NATIVE_WRITE << 4,
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[1] = DP_SET_POWER >> 8,
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[2] = DP_SET_POWER & 0xff,
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[3] = 1 - 1,
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[4] = DP_SET_POWER_D0,
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};
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u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK |
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EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK |
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EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK |
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EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK;
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BUILD_BUG_ON(sizeof(aux_msg) > 20);
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for (i = 0; i < sizeof(aux_msg); i += 4)
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I915_WRITE(EDP_PSR_AUX_DATA(dev_priv->psr.transcoder, i >> 2),
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intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
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aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
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/* Start with bits set for DDI_AUX_CTL register */
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aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg),
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aux_clock_divider);
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/* Select only valid bits for SRD_AUX_CTL */
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aux_ctl &= psr_aux_mask;
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I915_WRITE(EDP_PSR_AUX_CTL(dev_priv->psr.transcoder), aux_ctl);
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}
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static void intel_psr_enable_sink(struct intel_dp *intel_dp)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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u8 dpcd_val = DP_PSR_ENABLE;
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/* Enable ALPM at sink for psr2 */
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if (dev_priv->psr.psr2_enabled) {
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drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
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DP_ALPM_ENABLE);
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dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
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} else {
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if (dev_priv->psr.link_standby)
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dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
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if (INTEL_GEN(dev_priv) >= 8)
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dpcd_val |= DP_PSR_CRC_VERIFICATION;
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}
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drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
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drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
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}
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static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
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{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
u32 val = 0;
|
|
|
|
if (INTEL_GEN(dev_priv) >= 11)
|
|
val |= EDP_PSR_TP4_TIME_0US;
|
|
|
|
if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
|
|
val |= EDP_PSR_TP1_TIME_0us;
|
|
else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
|
|
val |= EDP_PSR_TP1_TIME_100us;
|
|
else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
|
|
val |= EDP_PSR_TP1_TIME_500us;
|
|
else
|
|
val |= EDP_PSR_TP1_TIME_2500us;
|
|
|
|
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
|
|
val |= EDP_PSR_TP2_TP3_TIME_0us;
|
|
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
|
|
val |= EDP_PSR_TP2_TP3_TIME_100us;
|
|
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
|
|
val |= EDP_PSR_TP2_TP3_TIME_500us;
|
|
else
|
|
val |= EDP_PSR_TP2_TP3_TIME_2500us;
|
|
|
|
if (intel_dp_source_supports_hbr2(intel_dp) &&
|
|
drm_dp_tps3_supported(intel_dp->dpcd))
|
|
val |= EDP_PSR_TP1_TP3_SEL;
|
|
else
|
|
val |= EDP_PSR_TP1_TP2_SEL;
|
|
|
|
return val;
|
|
}
|
|
|
|
static void hsw_activate_psr1(struct intel_dp *intel_dp)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
u32 max_sleep_time = 0x1f;
|
|
u32 val = EDP_PSR_ENABLE;
|
|
|
|
/* Let's use 6 as the minimum to cover all known cases including the
|
|
* off-by-one issue that HW has in some cases.
|
|
*/
|
|
int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
|
|
|
|
/* sink_sync_latency of 8 means source has to wait for more than 8
|
|
* frames, we'll go with 9 frames for now
|
|
*/
|
|
idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
|
|
val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
|
|
|
|
val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
|
|
if (IS_HASWELL(dev_priv))
|
|
val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
|
|
|
|
if (dev_priv->psr.link_standby)
|
|
val |= EDP_PSR_LINK_STANDBY;
|
|
|
|
val |= intel_psr1_get_tp_time(intel_dp);
|
|
|
|
if (INTEL_GEN(dev_priv) >= 8)
|
|
val |= EDP_PSR_CRC_ENABLE;
|
|
|
|
val |= (I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) &
|
|
EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK);
|
|
I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), val);
|
|
}
|
|
|
|
static void hsw_activate_psr2(struct intel_dp *intel_dp)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
u32 val;
|
|
|
|
/* Let's use 6 as the minimum to cover all known cases including the
|
|
* off-by-one issue that HW has in some cases.
|
|
*/
|
|
int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
|
|
|
|
idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
|
|
val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
|
|
|
|
val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
|
|
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
|
|
val |= EDP_Y_COORDINATE_ENABLE;
|
|
|
|
val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
|
|
|
|
if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
|
|
dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
|
|
val |= EDP_PSR2_TP2_TIME_50us;
|
|
else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
|
|
val |= EDP_PSR2_TP2_TIME_100us;
|
|
else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
|
|
val |= EDP_PSR2_TP2_TIME_500us;
|
|
else
|
|
val |= EDP_PSR2_TP2_TIME_2500us;
|
|
|
|
/*
|
|
* PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
|
|
* recommending keep this bit unset while PSR2 is enabled.
|
|
*/
|
|
I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), 0);
|
|
|
|
I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
|
|
}
|
|
|
|
static bool
|
|
transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
|
|
{
|
|
if (INTEL_GEN(dev_priv) < 9)
|
|
return false;
|
|
else if (INTEL_GEN(dev_priv) >= 12)
|
|
return trans == TRANSCODER_A;
|
|
else
|
|
return trans == TRANSCODER_EDP;
|
|
}
|
|
|
|
static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
|
|
{
|
|
if (!cstate || !cstate->base.active)
|
|
return 0;
|
|
|
|
return DIV_ROUND_UP(1000 * 1000,
|
|
drm_mode_vrefresh(&cstate->base.adjusted_mode));
|
|
}
|
|
|
|
static void psr2_program_idle_frames(struct drm_i915_private *dev_priv,
|
|
u32 idle_frames)
|
|
{
|
|
u32 val;
|
|
|
|
idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
|
|
val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
|
|
val &= ~EDP_PSR2_IDLE_FRAME_MASK;
|
|
val |= idle_frames;
|
|
I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
|
|
}
|
|
|
|
static void tgl_psr2_enable_dc3co(struct drm_i915_private *dev_priv)
|
|
{
|
|
psr2_program_idle_frames(dev_priv, 0);
|
|
intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO);
|
|
}
|
|
|
|
static void tgl_psr2_disable_dc3co(struct drm_i915_private *dev_priv)
|
|
{
|
|
int idle_frames;
|
|
|
|
intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
|
|
/*
|
|
* Restore PSR2 idle frame let's use 6 as the minimum to cover all known
|
|
* cases including the off-by-one issue that HW has in some cases.
|
|
*/
|
|
idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
|
|
idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
|
|
psr2_program_idle_frames(dev_priv, idle_frames);
|
|
}
|
|
|
|
static void tgl_dc5_idle_thread(struct work_struct *work)
|
|
{
|
|
struct drm_i915_private *dev_priv =
|
|
container_of(work, typeof(*dev_priv), psr.idle_work.work);
|
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
/* If delayed work is pending, it is not idle */
|
|
if (delayed_work_pending(&dev_priv->psr.idle_work))
|
|
goto unlock;
|
|
|
|
DRM_DEBUG_KMS("DC5/6 idle thread\n");
|
|
tgl_psr2_disable_dc3co(dev_priv);
|
|
unlock:
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
}
|
|
|
|
static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
|
|
{
|
|
if (!dev_priv->psr.dc3co_enabled)
|
|
return;
|
|
|
|
cancel_delayed_work(&dev_priv->psr.idle_work);
|
|
/* Before PSR2 exit disallow dc3co*/
|
|
tgl_psr2_disable_dc3co(dev_priv);
|
|
}
|
|
|
|
static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
|
|
struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay;
|
|
int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
|
|
int psr_max_h = 0, psr_max_v = 0;
|
|
|
|
if (!dev_priv->psr.sink_psr2_support)
|
|
return false;
|
|
|
|
if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
|
|
DRM_DEBUG_KMS("PSR2 not supported in transcoder %s\n",
|
|
transcoder_name(crtc_state->cpu_transcoder));
|
|
return false;
|
|
}
|
|
|
|
/*
|
|
* DSC and PSR2 cannot be enabled simultaneously. If a requested
|
|
* resolution requires DSC to be enabled, priority is given to DSC
|
|
* over PSR2.
|
|
*/
|
|
if (crtc_state->dsc.compression_enable) {
|
|
DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
|
|
return false;
|
|
}
|
|
|
|
if (INTEL_GEN(dev_priv) >= 12) {
|
|
psr_max_h = 5120;
|
|
psr_max_v = 3200;
|
|
} else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
|
|
psr_max_h = 4096;
|
|
psr_max_v = 2304;
|
|
} else if (IS_GEN(dev_priv, 9)) {
|
|
psr_max_h = 3640;
|
|
psr_max_v = 2304;
|
|
}
|
|
|
|
if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {
|
|
DRM_DEBUG_KMS("PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",
|
|
crtc_hdisplay, crtc_vdisplay,
|
|
psr_max_h, psr_max_v);
|
|
return false;
|
|
}
|
|
|
|
/*
|
|
* HW sends SU blocks of size four scan lines, which means the starting
|
|
* X coordinate and Y granularity requirements will always be met. We
|
|
* only need to validate the SU block width is a multiple of
|
|
* x granularity.
|
|
*/
|
|
if (crtc_hdisplay % dev_priv->psr.su_x_granularity) {
|
|
DRM_DEBUG_KMS("PSR2 not enabled, hdisplay(%d) not multiple of %d\n",
|
|
crtc_hdisplay, dev_priv->psr.su_x_granularity);
|
|
return false;
|
|
}
|
|
|
|
if (crtc_state->crc_enabled) {
|
|
DRM_DEBUG_KMS("PSR2 not enabled because it would inhibit pipe CRC calculation\n");
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
void intel_psr_compute_config(struct intel_dp *intel_dp,
|
|
struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
const struct drm_display_mode *adjusted_mode =
|
|
&crtc_state->base.adjusted_mode;
|
|
int psr_setup_time;
|
|
|
|
if (!CAN_PSR(dev_priv))
|
|
return;
|
|
|
|
if (intel_dp != dev_priv->psr.dp)
|
|
return;
|
|
|
|
/*
|
|
* HSW spec explicitly says PSR is tied to port A.
|
|
* BDW+ platforms have a instance of PSR registers per transcoder but
|
|
* for now it only supports one instance of PSR, so lets keep it
|
|
* hardcoded to PORT_A
|
|
*/
|
|
if (dig_port->base.port != PORT_A) {
|
|
DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
|
|
return;
|
|
}
|
|
|
|
if (dev_priv->psr.sink_not_reliable) {
|
|
DRM_DEBUG_KMS("PSR sink implementation is not reliable\n");
|
|
return;
|
|
}
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
|
|
DRM_DEBUG_KMS("PSR condition failed: Interlaced mode enabled\n");
|
|
return;
|
|
}
|
|
|
|
psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
|
|
if (psr_setup_time < 0) {
|
|
DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
|
|
intel_dp->psr_dpcd[1]);
|
|
return;
|
|
}
|
|
|
|
if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
|
|
adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
|
|
DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
|
|
psr_setup_time);
|
|
return;
|
|
}
|
|
|
|
crtc_state->has_psr = true;
|
|
crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
|
|
}
|
|
|
|
static void intel_psr_activate(struct intel_dp *intel_dp)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
|
|
if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder))
|
|
WARN_ON(I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE);
|
|
|
|
WARN_ON(I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE);
|
|
WARN_ON(dev_priv->psr.active);
|
|
lockdep_assert_held(&dev_priv->psr.lock);
|
|
|
|
/* psr1 and psr2 are mutually exclusive.*/
|
|
if (dev_priv->psr.psr2_enabled)
|
|
hsw_activate_psr2(intel_dp);
|
|
else
|
|
hsw_activate_psr1(intel_dp);
|
|
|
|
dev_priv->psr.active = true;
|
|
}
|
|
|
|
static void intel_psr_enable_source(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
|
|
u32 mask;
|
|
|
|
/* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
|
|
* use hardcoded values PSR AUX transactions
|
|
*/
|
|
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
|
hsw_psr_setup_aux(intel_dp);
|
|
|
|
if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
|
|
!IS_GEMINILAKE(dev_priv))) {
|
|
i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
|
|
u32 chicken = I915_READ(reg);
|
|
|
|
chicken |= PSR2_VSC_ENABLE_PROG_HEADER |
|
|
PSR2_ADD_VERTICAL_LINE_COUNT;
|
|
I915_WRITE(reg, chicken);
|
|
}
|
|
|
|
/*
|
|
* Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
|
|
* mask LPSP to avoid dependency on other drivers that might block
|
|
* runtime_pm besides preventing other hw tracking issues now we
|
|
* can rely on frontbuffer tracking.
|
|
*/
|
|
mask = EDP_PSR_DEBUG_MASK_MEMUP |
|
|
EDP_PSR_DEBUG_MASK_HPD |
|
|
EDP_PSR_DEBUG_MASK_LPSP |
|
|
EDP_PSR_DEBUG_MASK_MAX_SLEEP;
|
|
|
|
if (INTEL_GEN(dev_priv) < 11)
|
|
mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
|
|
|
|
I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask);
|
|
|
|
psr_irq_control(dev_priv);
|
|
}
|
|
|
|
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct intel_dp *intel_dp = dev_priv->psr.dp;
|
|
u32 val;
|
|
|
|
WARN_ON(dev_priv->psr.enabled);
|
|
|
|
dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
|
|
dev_priv->psr.busy_frontbuffer_bits = 0;
|
|
dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
|
|
dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
|
|
dev_priv->psr.dc3co_exit_delay = intel_get_frame_time_us(crtc_state);
|
|
dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
|
|
|
|
/*
|
|
* If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
|
|
* will still keep the error set even after the reset done in the
|
|
* irq_preinstall and irq_uninstall hooks.
|
|
* And enabling in this situation cause the screen to freeze in the
|
|
* first time that PSR HW tries to activate so lets keep PSR disabled
|
|
* to avoid any rendering problems.
|
|
*/
|
|
if (INTEL_GEN(dev_priv) >= 12) {
|
|
val = I915_READ(TRANS_PSR_IIR(dev_priv->psr.transcoder));
|
|
val &= EDP_PSR_ERROR(0);
|
|
} else {
|
|
val = I915_READ(EDP_PSR_IIR);
|
|
val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
|
|
}
|
|
if (val) {
|
|
dev_priv->psr.sink_not_reliable = true;
|
|
DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n");
|
|
return;
|
|
}
|
|
|
|
DRM_DEBUG_KMS("Enabling PSR%s\n",
|
|
dev_priv->psr.psr2_enabled ? "2" : "1");
|
|
intel_psr_setup_vsc(intel_dp, crtc_state);
|
|
intel_psr_enable_sink(intel_dp);
|
|
intel_psr_enable_source(intel_dp, crtc_state);
|
|
dev_priv->psr.enabled = true;
|
|
|
|
intel_psr_activate(intel_dp);
|
|
}
|
|
|
|
/**
|
|
* intel_psr_enable - Enable PSR
|
|
* @intel_dp: Intel DP
|
|
* @crtc_state: new CRTC state
|
|
*
|
|
* This function can only be called after the pipe is fully trained and enabled.
|
|
*/
|
|
void intel_psr_enable(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
|
|
if (!crtc_state->has_psr)
|
|
return;
|
|
|
|
if (WARN_ON(!CAN_PSR(dev_priv)))
|
|
return;
|
|
|
|
WARN_ON(dev_priv->drrs.dp);
|
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
|
|
if (!psr_global_enabled(dev_priv->psr.debug)) {
|
|
DRM_DEBUG_KMS("PSR disabled by flag\n");
|
|
goto unlock;
|
|
}
|
|
|
|
intel_psr_enable_locked(dev_priv, crtc_state);
|
|
|
|
unlock:
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
}
|
|
|
|
static void intel_psr_exit(struct drm_i915_private *dev_priv)
|
|
{
|
|
u32 val;
|
|
|
|
if (!dev_priv->psr.active) {
|
|
if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) {
|
|
val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
|
|
WARN_ON(val & EDP_PSR2_ENABLE);
|
|
}
|
|
|
|
val = I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder));
|
|
WARN_ON(val & EDP_PSR_ENABLE);
|
|
|
|
return;
|
|
}
|
|
|
|
if (dev_priv->psr.psr2_enabled) {
|
|
tgl_disallow_dc3co_on_psr2_exit(dev_priv);
|
|
val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
|
|
WARN_ON(!(val & EDP_PSR2_ENABLE));
|
|
val &= ~EDP_PSR2_ENABLE;
|
|
I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
|
|
} else {
|
|
val = I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder));
|
|
WARN_ON(!(val & EDP_PSR_ENABLE));
|
|
val &= ~EDP_PSR_ENABLE;
|
|
I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), val);
|
|
}
|
|
dev_priv->psr.active = false;
|
|
}
|
|
|
|
static void intel_psr_disable_locked(struct intel_dp *intel_dp)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
i915_reg_t psr_status;
|
|
u32 psr_status_mask;
|
|
|
|
lockdep_assert_held(&dev_priv->psr.lock);
|
|
|
|
if (!dev_priv->psr.enabled)
|
|
return;
|
|
|
|
DRM_DEBUG_KMS("Disabling PSR%s\n",
|
|
dev_priv->psr.psr2_enabled ? "2" : "1");
|
|
|
|
intel_psr_exit(dev_priv);
|
|
|
|
if (dev_priv->psr.psr2_enabled) {
|
|
psr_status = EDP_PSR2_STATUS(dev_priv->psr.transcoder);
|
|
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
|
|
} else {
|
|
psr_status = EDP_PSR_STATUS(dev_priv->psr.transcoder);
|
|
psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
|
|
}
|
|
|
|
/* Wait till PSR is idle */
|
|
if (intel_de_wait_for_clear(dev_priv, psr_status,
|
|
psr_status_mask, 2000))
|
|
DRM_ERROR("Timed out waiting PSR idle state\n");
|
|
|
|
/* Disable PSR on Sink */
|
|
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
|
|
|
|
dev_priv->psr.enabled = false;
|
|
}
|
|
|
|
/**
|
|
* intel_psr_disable - Disable PSR
|
|
* @intel_dp: Intel DP
|
|
* @old_crtc_state: old CRTC state
|
|
*
|
|
* This function needs to be called before disabling pipe.
|
|
*/
|
|
void intel_psr_disable(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *old_crtc_state)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
|
|
if (!old_crtc_state->has_psr)
|
|
return;
|
|
|
|
if (WARN_ON(!CAN_PSR(dev_priv)))
|
|
return;
|
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
|
|
intel_psr_disable_locked(intel_dp);
|
|
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
cancel_work_sync(&dev_priv->psr.work);
|
|
cancel_delayed_work_sync(&dev_priv->psr.idle_work);
|
|
}
|
|
|
|
static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
|
|
{
|
|
if (INTEL_GEN(dev_priv) >= 9)
|
|
/*
|
|
* Display WA #0884: skl+
|
|
* This documented WA for bxt can be safely applied
|
|
* broadly so we can force HW tracking to exit PSR
|
|
* instead of disabling and re-enabling.
|
|
* Workaround tells us to write 0 to CUR_SURFLIVE_A,
|
|
* but it makes more sense write to the current active
|
|
* pipe.
|
|
*/
|
|
I915_WRITE(CURSURFLIVE(dev_priv->psr.pipe), 0);
|
|
else
|
|
/*
|
|
* A write to CURSURFLIVE do not cause HW tracking to exit PSR
|
|
* on older gens so doing the manual exit instead.
|
|
*/
|
|
intel_psr_exit(dev_priv);
|
|
}
|
|
|
|
/**
|
|
* intel_psr_update - Update PSR state
|
|
* @intel_dp: Intel DP
|
|
* @crtc_state: new CRTC state
|
|
*
|
|
* This functions will update PSR states, disabling, enabling or switching PSR
|
|
* version when executing fastsets. For full modeset, intel_psr_disable() and
|
|
* intel_psr_enable() should be called instead.
|
|
*/
|
|
void intel_psr_update(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
struct i915_psr *psr = &dev_priv->psr;
|
|
bool enable, psr2_enable;
|
|
|
|
if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp)
|
|
return;
|
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
|
|
enable = crtc_state->has_psr && psr_global_enabled(psr->debug);
|
|
psr2_enable = intel_psr2_enabled(dev_priv, crtc_state);
|
|
|
|
if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) {
|
|
/* Force a PSR exit when enabling CRC to avoid CRC timeouts */
|
|
if (crtc_state->crc_enabled && psr->enabled)
|
|
psr_force_hw_tracking_exit(dev_priv);
|
|
else if (INTEL_GEN(dev_priv) < 9 && psr->enabled) {
|
|
/*
|
|
* Activate PSR again after a force exit when enabling
|
|
* CRC in older gens
|
|
*/
|
|
if (!dev_priv->psr.active &&
|
|
!dev_priv->psr.busy_frontbuffer_bits)
|
|
schedule_work(&dev_priv->psr.work);
|
|
}
|
|
|
|
goto unlock;
|
|
}
|
|
|
|
if (psr->enabled)
|
|
intel_psr_disable_locked(intel_dp);
|
|
|
|
if (enable)
|
|
intel_psr_enable_locked(dev_priv, crtc_state);
|
|
|
|
unlock:
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
}
|
|
|
|
/**
|
|
* intel_psr_wait_for_idle - wait for PSR1 to idle
|
|
* @new_crtc_state: new CRTC state
|
|
* @out_value: PSR status in case of failure
|
|
*
|
|
* This function is expected to be called from pipe_update_start() where it is
|
|
* not expected to race with PSR enable or disable.
|
|
*
|
|
* Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
|
|
*/
|
|
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
|
|
u32 *out_value)
|
|
{
|
|
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
|
|
|
if (!dev_priv->psr.enabled || !new_crtc_state->has_psr)
|
|
return 0;
|
|
|
|
/* FIXME: Update this for PSR2 if we need to wait for idle */
|
|
if (READ_ONCE(dev_priv->psr.psr2_enabled))
|
|
return 0;
|
|
|
|
/*
|
|
* From bspec: Panel Self Refresh (BDW+)
|
|
* Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
|
|
* exit training time + 1.5 ms of aux channel handshake. 50 ms is
|
|
* defensive enough to cover everything.
|
|
*/
|
|
|
|
return __intel_wait_for_register(&dev_priv->uncore,
|
|
EDP_PSR_STATUS(dev_priv->psr.transcoder),
|
|
EDP_PSR_STATUS_STATE_MASK,
|
|
EDP_PSR_STATUS_STATE_IDLE, 2, 50,
|
|
out_value);
|
|
}
|
|
|
|
static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
|
|
{
|
|
i915_reg_t reg;
|
|
u32 mask;
|
|
int err;
|
|
|
|
if (!dev_priv->psr.enabled)
|
|
return false;
|
|
|
|
if (dev_priv->psr.psr2_enabled) {
|
|
reg = EDP_PSR2_STATUS(dev_priv->psr.transcoder);
|
|
mask = EDP_PSR2_STATUS_STATE_MASK;
|
|
} else {
|
|
reg = EDP_PSR_STATUS(dev_priv->psr.transcoder);
|
|
mask = EDP_PSR_STATUS_STATE_MASK;
|
|
}
|
|
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
|
|
err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
|
|
if (err)
|
|
DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
|
|
|
|
/* After the unlocked wait, verify that PSR is still wanted! */
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
return err == 0 && dev_priv->psr.enabled;
|
|
}
|
|
|
|
static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct drm_device *dev = &dev_priv->drm;
|
|
struct drm_modeset_acquire_ctx ctx;
|
|
struct drm_atomic_state *state;
|
|
struct intel_crtc *crtc;
|
|
int err;
|
|
|
|
state = drm_atomic_state_alloc(dev);
|
|
if (!state)
|
|
return -ENOMEM;
|
|
|
|
drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
|
|
state->acquire_ctx = &ctx;
|
|
|
|
retry:
|
|
for_each_intel_crtc(dev, crtc) {
|
|
struct intel_crtc_state *crtc_state =
|
|
intel_atomic_get_crtc_state(state, crtc);
|
|
|
|
if (IS_ERR(crtc_state)) {
|
|
err = PTR_ERR(crtc_state);
|
|
goto error;
|
|
}
|
|
|
|
if (crtc_state->base.active && crtc_state->has_psr) {
|
|
/* Mark mode as changed to trigger a pipe->update() */
|
|
crtc_state->base.mode_changed = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
err = drm_atomic_commit(state);
|
|
|
|
error:
|
|
if (err == -EDEADLK) {
|
|
drm_atomic_state_clear(state);
|
|
err = drm_modeset_backoff(&ctx);
|
|
if (!err)
|
|
goto retry;
|
|
}
|
|
|
|
drm_modeset_drop_locks(&ctx);
|
|
drm_modeset_acquire_fini(&ctx);
|
|
drm_atomic_state_put(state);
|
|
|
|
return err;
|
|
}
|
|
|
|
int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val)
|
|
{
|
|
const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
|
|
u32 old_mode;
|
|
int ret;
|
|
|
|
if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
|
|
mode > I915_PSR_DEBUG_FORCE_PSR1) {
|
|
DRM_DEBUG_KMS("Invalid debug mask %llx\n", val);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = mutex_lock_interruptible(&dev_priv->psr.lock);
|
|
if (ret)
|
|
return ret;
|
|
|
|
old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK;
|
|
dev_priv->psr.debug = val;
|
|
|
|
/*
|
|
* Do it right away if it's already enabled, otherwise it will be done
|
|
* when enabling the source.
|
|
*/
|
|
if (dev_priv->psr.enabled)
|
|
psr_irq_control(dev_priv);
|
|
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
|
|
if (old_mode != mode)
|
|
ret = intel_psr_fastset_force(dev_priv);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void intel_psr_handle_irq(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct i915_psr *psr = &dev_priv->psr;
|
|
|
|
intel_psr_disable_locked(psr->dp);
|
|
psr->sink_not_reliable = true;
|
|
/* let's make sure that sink is awaken */
|
|
drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
|
|
}
|
|
|
|
static void intel_psr_work(struct work_struct *work)
|
|
{
|
|
struct drm_i915_private *dev_priv =
|
|
container_of(work, typeof(*dev_priv), psr.work);
|
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
|
|
if (!dev_priv->psr.enabled)
|
|
goto unlock;
|
|
|
|
if (READ_ONCE(dev_priv->psr.irq_aux_error))
|
|
intel_psr_handle_irq(dev_priv);
|
|
|
|
/*
|
|
* We have to make sure PSR is ready for re-enable
|
|
* otherwise it keeps disabled until next full enable/disable cycle.
|
|
* PSR might take some time to get fully disabled
|
|
* and be ready for re-enable.
|
|
*/
|
|
if (!__psr_wait_for_idle_locked(dev_priv))
|
|
goto unlock;
|
|
|
|
/*
|
|
* The delayed work can race with an invalidate hence we need to
|
|
* recheck. Since psr_flush first clears this and then reschedules we
|
|
* won't ever miss a flush when bailing out here.
|
|
*/
|
|
if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active)
|
|
goto unlock;
|
|
|
|
intel_psr_activate(dev_priv->psr.dp);
|
|
unlock:
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
}
|
|
|
|
/**
|
|
* intel_psr_invalidate - Invalidade PSR
|
|
* @dev_priv: i915 device
|
|
* @frontbuffer_bits: frontbuffer plane tracking bits
|
|
* @origin: which operation caused the invalidate
|
|
*
|
|
* Since the hardware frontbuffer tracking has gaps we need to integrate
|
|
* with the software frontbuffer tracking. This function gets called every
|
|
* time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
|
|
* disabled if the frontbuffer mask contains a buffer relevant to PSR.
|
|
*
|
|
* Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
|
|
*/
|
|
void intel_psr_invalidate(struct drm_i915_private *dev_priv,
|
|
unsigned frontbuffer_bits, enum fb_op_origin origin)
|
|
{
|
|
if (!CAN_PSR(dev_priv))
|
|
return;
|
|
|
|
if (origin == ORIGIN_FLIP)
|
|
return;
|
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
if (!dev_priv->psr.enabled) {
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
return;
|
|
}
|
|
|
|
frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe);
|
|
dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
|
|
|
|
if (frontbuffer_bits)
|
|
intel_psr_exit(dev_priv);
|
|
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
}
|
|
|
|
/*
|
|
* When we will be completely rely on PSR2 S/W tracking in future,
|
|
* intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
|
|
* event also therefore tgl_dc3co_flush() require to be changed
|
|
* accrodingly in future.
|
|
*/
|
|
static void
|
|
tgl_dc3co_flush(struct drm_i915_private *dev_priv,
|
|
unsigned int frontbuffer_bits, enum fb_op_origin origin)
|
|
{
|
|
u32 delay;
|
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
|
|
if (!dev_priv->psr.dc3co_enabled)
|
|
goto unlock;
|
|
|
|
if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active)
|
|
goto unlock;
|
|
|
|
/*
|
|
* At every frontbuffer flush flip event modified delay of delayed work,
|
|
* when delayed work schedules that means display has been idle.
|
|
*/
|
|
if (!(frontbuffer_bits &
|
|
INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe)))
|
|
goto unlock;
|
|
|
|
tgl_psr2_enable_dc3co(dev_priv);
|
|
/* DC5/DC6 required idle frames = 6 */
|
|
delay = 6 * dev_priv->psr.dc3co_exit_delay;
|
|
mod_delayed_work(system_wq, &dev_priv->psr.idle_work,
|
|
usecs_to_jiffies(delay));
|
|
|
|
unlock:
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
}
|
|
|
|
/**
|
|
* intel_psr_flush - Flush PSR
|
|
* @dev_priv: i915 device
|
|
* @frontbuffer_bits: frontbuffer plane tracking bits
|
|
* @origin: which operation caused the flush
|
|
*
|
|
* Since the hardware frontbuffer tracking has gaps we need to integrate
|
|
* with the software frontbuffer tracking. This function gets called every
|
|
* time frontbuffer rendering has completed and flushed out to memory. PSR
|
|
* can be enabled again if no other frontbuffer relevant to PSR is dirty.
|
|
*
|
|
* Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
|
|
*/
|
|
void intel_psr_flush(struct drm_i915_private *dev_priv,
|
|
unsigned frontbuffer_bits, enum fb_op_origin origin)
|
|
{
|
|
if (!CAN_PSR(dev_priv))
|
|
return;
|
|
|
|
if (origin == ORIGIN_FLIP) {
|
|
tgl_dc3co_flush(dev_priv, frontbuffer_bits, origin);
|
|
return;
|
|
}
|
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
if (!dev_priv->psr.enabled) {
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
return;
|
|
}
|
|
|
|
frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe);
|
|
dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
|
|
|
|
/* By definition flush = invalidate + flush */
|
|
if (frontbuffer_bits)
|
|
psr_force_hw_tracking_exit(dev_priv);
|
|
|
|
if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
|
|
schedule_work(&dev_priv->psr.work);
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
}
|
|
|
|
/**
|
|
* intel_psr_init - Init basic PSR work and mutex.
|
|
* @dev_priv: i915 device private
|
|
*
|
|
* This function is called only once at driver load to initialize basic
|
|
* PSR stuff.
|
|
*/
|
|
void intel_psr_init(struct drm_i915_private *dev_priv)
|
|
{
|
|
if (!HAS_PSR(dev_priv))
|
|
return;
|
|
|
|
if (!dev_priv->psr.sink_support)
|
|
return;
|
|
|
|
if (IS_HASWELL(dev_priv))
|
|
/*
|
|
* HSW don't have PSR registers on the same space as transcoder
|
|
* so set this to a value that when subtract to the register
|
|
* in transcoder space results in the right offset for HSW
|
|
*/
|
|
dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE;
|
|
|
|
if (i915_modparams.enable_psr == -1)
|
|
if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
|
|
i915_modparams.enable_psr = 0;
|
|
|
|
/* Set link_standby x link_off defaults */
|
|
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
|
/* HSW and BDW require workarounds that we don't implement. */
|
|
dev_priv->psr.link_standby = false;
|
|
else if (INTEL_GEN(dev_priv) < 12)
|
|
/* For new platforms up to TGL let's respect VBT back again */
|
|
dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
|
|
|
|
INIT_WORK(&dev_priv->psr.work, intel_psr_work);
|
|
INIT_DELAYED_WORK(&dev_priv->psr.idle_work, tgl_dc5_idle_thread);
|
|
mutex_init(&dev_priv->psr.lock);
|
|
}
|
|
|
|
void intel_psr_short_pulse(struct intel_dp *intel_dp)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
struct i915_psr *psr = &dev_priv->psr;
|
|
u8 val;
|
|
const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
|
|
DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
|
|
DP_PSR_LINK_CRC_ERROR;
|
|
|
|
if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
|
|
return;
|
|
|
|
mutex_lock(&psr->lock);
|
|
|
|
if (!psr->enabled || psr->dp != intel_dp)
|
|
goto exit;
|
|
|
|
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) {
|
|
DRM_ERROR("PSR_STATUS dpcd read failed\n");
|
|
goto exit;
|
|
}
|
|
|
|
if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) {
|
|
DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");
|
|
intel_psr_disable_locked(intel_dp);
|
|
psr->sink_not_reliable = true;
|
|
}
|
|
|
|
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) {
|
|
DRM_ERROR("PSR_ERROR_STATUS dpcd read failed\n");
|
|
goto exit;
|
|
}
|
|
|
|
if (val & DP_PSR_RFB_STORAGE_ERROR)
|
|
DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n");
|
|
if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
|
|
DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n");
|
|
if (val & DP_PSR_LINK_CRC_ERROR)
|
|
DRM_DEBUG_KMS("PSR Link CRC error, disabling PSR\n");
|
|
|
|
if (val & ~errors)
|
|
DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n",
|
|
val & ~errors);
|
|
if (val & errors) {
|
|
intel_psr_disable_locked(intel_dp);
|
|
psr->sink_not_reliable = true;
|
|
}
|
|
/* clear status register */
|
|
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
|
|
exit:
|
|
mutex_unlock(&psr->lock);
|
|
}
|
|
|
|
bool intel_psr_enabled(struct intel_dp *intel_dp)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
bool ret;
|
|
|
|
if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
|
|
return false;
|
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled);
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
|
|
return ret;
|
|
}
|