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![David Howells](/assets/img/avatar_default.png)
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead of passing regs around manually through all ~1800 interrupt handlers in the Linux kernel. The regs pointer is used in few places, but it potentially costs both stack space and code to pass it around. On the FRV arch, removing the regs parameter from all the genirq function results in a 20% speed up of the IRQ exit path (ie: from leaving timer_interrupt() to leaving do_IRQ()). Where appropriate, an arch may override the generic storage facility and do something different with the variable. On FRV, for instance, the address is maintained in GR28 at all times inside the kernel as part of general exception handling. Having looked over the code, it appears that the parameter may be handed down through up to twenty or so layers of functions. Consider a USB character device attached to a USB hub, attached to a USB controller that posts its interrupts through a cascaded auxiliary interrupt controller. A character device driver may want to pass regs to the sysrq handler through the input layer which adds another few layers of parameter passing. I've build this code with allyesconfig for x86_64 and i386. I've runtested the main part of the code on FRV and i386, though I can't test most of the drivers. I've also done partial conversion for powerpc and MIPS - these at least compile with minimal configurations. This will affect all archs. Mostly the changes should be relatively easy. Take do_IRQ(), store the regs pointer at the beginning, saving the old one: struct pt_regs *old_regs = set_irq_regs(regs); And put the old one back at the end: set_irq_regs(old_regs); Don't pass regs through to generic_handle_irq() or __do_IRQ(). In timer_interrupt(), this sort of change will be necessary: - update_process_times(user_mode(regs)); - profile_tick(CPU_PROFILING, regs); + update_process_times(user_mode(get_irq_regs())); + profile_tick(CPU_PROFILING); I'd like to move update_process_times()'s use of get_irq_regs() into itself, except that i386, alone of the archs, uses something other than user_mode(). Some notes on the interrupt handling in the drivers: (*) input_dev() is now gone entirely. The regs pointer is no longer stored in the input_dev struct. (*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does something different depending on whether it's been supplied with a regs pointer or not. (*) Various IRQ handler function pointers have been moved to type irq_handler_t. Signed-Off-By: David Howells <dhowells@redhat.com> (cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
976 lines
23 KiB
C
976 lines
23 KiB
C
/*
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* linux/drivers/mmc/at91_mci.c - ATMEL AT91RM9200 MCI Driver
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*
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* Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved
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*
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* Copyright (C) 2006 Malcolm Noyes
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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This is the AT91RM9200 MCI driver that has been tested with both MMC cards
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and SD-cards. Boards that support write protect are now supported.
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The CCAT91SBC001 board does not support SD cards.
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The three entry points are at91_mci_request, at91_mci_set_ios
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and at91_mci_get_ro.
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SET IOS
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This configures the device to put it into the correct mode and clock speed
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required.
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MCI REQUEST
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MCI request processes the commands sent in the mmc_request structure. This
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can consist of a processing command and a stop command in the case of
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multiple block transfers.
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There are three main types of request, commands, reads and writes.
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Commands are straight forward. The command is submitted to the controller and
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the request function returns. When the controller generates an interrupt to indicate
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the command is finished, the response to the command are read and the mmc_request_done
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function called to end the request.
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Reads and writes work in a similar manner to normal commands but involve the PDC (DMA)
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controller to manage the transfers.
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A read is done from the controller directly to the scatterlist passed in from the request.
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Due to a bug in the controller, when a read is completed, all the words are byte
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swapped in the scatterlist buffers.
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The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY
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A write is slightly different in that the bytes to write are read from the scatterlist
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into a dma memory buffer (this is in case the source buffer should be read only). The
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entire write buffer is then done from this single dma memory buffer.
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The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY
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GET RO
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Gets the status of the write protect pin, if available.
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/dma-mapping.h>
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#include <linux/clk.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/protocol.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mach/mmc.h>
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#include <asm/arch/board.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91rm9200_mci.h>
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#include <asm/arch/at91rm9200_pdc.h>
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#define DRIVER_NAME "at91_mci"
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#undef SUPPORT_4WIRE
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static struct clk *mci_clk;
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#define FL_SENT_COMMAND (1 << 0)
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#define FL_SENT_STOP (1 << 1)
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/*
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* Read from a MCI register.
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*/
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static inline unsigned long at91_mci_read(unsigned int reg)
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{
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void __iomem *mci_base = (void __iomem *)AT91_VA_BASE_MCI;
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return __raw_readl(mci_base + reg);
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}
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/*
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* Write to a MCI register.
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*/
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static inline void at91_mci_write(unsigned int reg, unsigned long value)
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{
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void __iomem *mci_base = (void __iomem *)AT91_VA_BASE_MCI;
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__raw_writel(value, mci_base + reg);
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}
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/*
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* Low level type for this driver
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*/
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struct at91mci_host
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{
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struct mmc_host *mmc;
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struct mmc_command *cmd;
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struct mmc_request *request;
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struct at91_mmc_data *board;
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int present;
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/*
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* Flag indicating when the command has been sent. This is used to
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* work out whether or not to send the stop
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*/
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unsigned int flags;
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/* flag for current bus settings */
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u32 bus_mode;
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/* DMA buffer used for transmitting */
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unsigned int* buffer;
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dma_addr_t physical_address;
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unsigned int total_length;
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/* Latest in the scatterlist that has been enabled for transfer, but not freed */
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int in_use_index;
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/* Latest in the scatterlist that has been enabled for transfer */
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int transfer_index;
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};
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/*
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* Copy from sg to a dma block - used for transfers
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*/
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static inline void at91mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data)
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{
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unsigned int len, i, size;
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unsigned *dmabuf = host->buffer;
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size = host->total_length;
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len = data->sg_len;
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/*
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* Just loop through all entries. Size might not
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* be the entire list though so make sure that
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* we do not transfer too much.
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*/
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for (i = 0; i < len; i++) {
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struct scatterlist *sg;
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int amount;
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int index;
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unsigned int *sgbuffer;
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sg = &data->sg[i];
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sgbuffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset;
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amount = min(size, sg->length);
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size -= amount;
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amount /= 4;
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for (index = 0; index < amount; index++)
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*dmabuf++ = swab32(sgbuffer[index]);
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kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
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if (size == 0)
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break;
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}
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/*
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* Check that we didn't get a request to transfer
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* more data than can fit into the SG list.
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*/
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BUG_ON(size != 0);
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}
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/*
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* Prepare a dma read
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*/
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static void at91mci_pre_dma_read(struct at91mci_host *host)
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{
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int i;
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struct scatterlist *sg;
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struct mmc_command *cmd;
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struct mmc_data *data;
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pr_debug("pre dma read\n");
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cmd = host->cmd;
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if (!cmd) {
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pr_debug("no command\n");
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return;
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}
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data = cmd->data;
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if (!data) {
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pr_debug("no data\n");
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return;
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}
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for (i = 0; i < 2; i++) {
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/* nothing left to transfer */
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if (host->transfer_index >= data->sg_len) {
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pr_debug("Nothing left to transfer (index = %d)\n", host->transfer_index);
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break;
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}
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/* Check to see if this needs filling */
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if (i == 0) {
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if (at91_mci_read(AT91_PDC_RCR) != 0) {
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pr_debug("Transfer active in current\n");
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continue;
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}
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}
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else {
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if (at91_mci_read(AT91_PDC_RNCR) != 0) {
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pr_debug("Transfer active in next\n");
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continue;
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}
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}
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/* Setup the next transfer */
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pr_debug("Using transfer index %d\n", host->transfer_index);
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sg = &data->sg[host->transfer_index++];
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pr_debug("sg = %p\n", sg);
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sg->dma_address = dma_map_page(NULL, sg->page, sg->offset, sg->length, DMA_FROM_DEVICE);
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pr_debug("dma address = %08X, length = %d\n", sg->dma_address, sg->length);
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if (i == 0) {
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at91_mci_write(AT91_PDC_RPR, sg->dma_address);
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at91_mci_write(AT91_PDC_RCR, sg->length / 4);
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}
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else {
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at91_mci_write(AT91_PDC_RNPR, sg->dma_address);
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at91_mci_write(AT91_PDC_RNCR, sg->length / 4);
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}
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}
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pr_debug("pre dma read done\n");
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}
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/*
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* Handle after a dma read
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*/
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static void at91mci_post_dma_read(struct at91mci_host *host)
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{
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struct mmc_command *cmd;
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struct mmc_data *data;
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pr_debug("post dma read\n");
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cmd = host->cmd;
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if (!cmd) {
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pr_debug("no command\n");
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return;
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}
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data = cmd->data;
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if (!data) {
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pr_debug("no data\n");
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return;
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}
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while (host->in_use_index < host->transfer_index) {
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unsigned int *buffer;
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int index;
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int len;
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struct scatterlist *sg;
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pr_debug("finishing index %d\n", host->in_use_index);
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sg = &data->sg[host->in_use_index++];
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pr_debug("Unmapping page %08X\n", sg->dma_address);
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dma_unmap_page(NULL, sg->dma_address, sg->length, DMA_FROM_DEVICE);
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/* Swap the contents of the buffer */
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buffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset;
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pr_debug("buffer = %p, length = %d\n", buffer, sg->length);
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data->bytes_xfered += sg->length;
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len = sg->length / 4;
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for (index = 0; index < len; index++) {
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buffer[index] = swab32(buffer[index]);
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}
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kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
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flush_dcache_page(sg->page);
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}
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/* Is there another transfer to trigger? */
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if (host->transfer_index < data->sg_len)
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at91mci_pre_dma_read(host);
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else {
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at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF);
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at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
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}
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pr_debug("post dma read done\n");
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}
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/*
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* Handle transmitted data
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*/
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static void at91_mci_handle_transmitted(struct at91mci_host *host)
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{
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struct mmc_command *cmd;
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struct mmc_data *data;
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pr_debug("Handling the transmit\n");
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/* Disable the transfer */
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at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
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/* Now wait for cmd ready */
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at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE);
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at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
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cmd = host->cmd;
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if (!cmd) return;
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data = cmd->data;
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if (!data) return;
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data->bytes_xfered = host->total_length;
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}
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/*
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* Enable the controller
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*/
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static void at91_mci_enable(void)
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{
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at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
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at91_mci_write(AT91_MCI_IDR, 0xFFFFFFFF);
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at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
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at91_mci_write(AT91_MCI_MR, 0x834A);
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at91_mci_write(AT91_MCI_SDCR, 0x0);
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}
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/*
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* Disable the controller
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*/
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static void at91_mci_disable(void)
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{
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at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
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}
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/*
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* Send a command
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* return the interrupts to enable
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*/
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static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd)
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{
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unsigned int cmdr, mr;
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unsigned int block_length;
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struct mmc_data *data = cmd->data;
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unsigned int blocks;
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unsigned int ier = 0;
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host->cmd = cmd;
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/* Not sure if this is needed */
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#if 0
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if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) {
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pr_debug("Clearing timeout\n");
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at91_mci_write(AT91_MCI_ARGR, 0);
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at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD);
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while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) {
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/* spin */
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pr_debug("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR));
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}
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}
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#endif
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cmdr = cmd->opcode;
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if (mmc_resp_type(cmd) == MMC_RSP_NONE)
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cmdr |= AT91_MCI_RSPTYP_NONE;
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else {
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/* if a response is expected then allow maximum response latancy */
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cmdr |= AT91_MCI_MAXLAT;
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/* set 136 bit response for R2, 48 bit response otherwise */
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if (mmc_resp_type(cmd) == MMC_RSP_R2)
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cmdr |= AT91_MCI_RSPTYP_136;
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else
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cmdr |= AT91_MCI_RSPTYP_48;
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}
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if (data) {
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block_length = data->blksz;
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blocks = data->blocks;
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/* always set data start - also set direction flag for read */
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if (data->flags & MMC_DATA_READ)
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cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START);
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else if (data->flags & MMC_DATA_WRITE)
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cmdr |= AT91_MCI_TRCMD_START;
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if (data->flags & MMC_DATA_STREAM)
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cmdr |= AT91_MCI_TRTYP_STREAM;
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if (data->flags & MMC_DATA_MULTI)
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cmdr |= AT91_MCI_TRTYP_MULTIPLE;
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}
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else {
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block_length = 0;
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blocks = 0;
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}
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if (cmd->opcode == MMC_STOP_TRANSMISSION)
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cmdr |= AT91_MCI_TRCMD_STOP;
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if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
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cmdr |= AT91_MCI_OPDCMD;
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/*
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* Set the arguments and send the command
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*/
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pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08lX)\n",
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cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR));
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if (!data) {
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at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS);
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at91_mci_write(AT91_PDC_RPR, 0);
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at91_mci_write(AT91_PDC_RCR, 0);
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at91_mci_write(AT91_PDC_RNPR, 0);
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at91_mci_write(AT91_PDC_RNCR, 0);
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at91_mci_write(AT91_PDC_TPR, 0);
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at91_mci_write(AT91_PDC_TCR, 0);
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at91_mci_write(AT91_PDC_TNPR, 0);
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at91_mci_write(AT91_PDC_TNCR, 0);
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at91_mci_write(AT91_MCI_ARGR, cmd->arg);
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at91_mci_write(AT91_MCI_CMDR, cmdr);
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return AT91_MCI_CMDRDY;
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}
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mr = at91_mci_read(AT91_MCI_MR) & 0x7fff; /* zero block length and PDC mode */
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at91_mci_write(AT91_MCI_MR, mr | (block_length << 16) | AT91_MCI_PDCMODE);
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/*
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* Disable the PDC controller
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*/
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at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
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if (cmdr & AT91_MCI_TRCMD_START) {
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data->bytes_xfered = 0;
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host->transfer_index = 0;
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host->in_use_index = 0;
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if (cmdr & AT91_MCI_TRDIR) {
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/*
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* Handle a read
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*/
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host->buffer = NULL;
|
|
host->total_length = 0;
|
|
|
|
at91mci_pre_dma_read(host);
|
|
ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
|
|
}
|
|
else {
|
|
/*
|
|
* Handle a write
|
|
*/
|
|
host->total_length = block_length * blocks;
|
|
host->buffer = dma_alloc_coherent(NULL,
|
|
host->total_length,
|
|
&host->physical_address, GFP_KERNEL);
|
|
|
|
at91mci_sg_to_dma(host, data);
|
|
|
|
pr_debug("Transmitting %d bytes\n", host->total_length);
|
|
|
|
at91_mci_write(AT91_PDC_TPR, host->physical_address);
|
|
at91_mci_write(AT91_PDC_TCR, host->total_length / 4);
|
|
ier = AT91_MCI_TXBUFE;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Send the command and then enable the PDC - not the other way round as
|
|
* the data sheet says
|
|
*/
|
|
|
|
at91_mci_write(AT91_MCI_ARGR, cmd->arg);
|
|
at91_mci_write(AT91_MCI_CMDR, cmdr);
|
|
|
|
if (cmdr & AT91_MCI_TRCMD_START) {
|
|
if (cmdr & AT91_MCI_TRDIR)
|
|
at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN);
|
|
else
|
|
at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN);
|
|
}
|
|
return ier;
|
|
}
|
|
|
|
/*
|
|
* Wait for a command to complete
|
|
*/
|
|
static void at91mci_process_command(struct at91mci_host *host, struct mmc_command *cmd)
|
|
{
|
|
unsigned int ier;
|
|
|
|
ier = at91_mci_send_command(host, cmd);
|
|
|
|
pr_debug("setting ier to %08X\n", ier);
|
|
|
|
/* Stop on errors or the required value */
|
|
at91_mci_write(AT91_MCI_IER, 0xffff0000 | ier);
|
|
}
|
|
|
|
/*
|
|
* Process the next step in the request
|
|
*/
|
|
static void at91mci_process_next(struct at91mci_host *host)
|
|
{
|
|
if (!(host->flags & FL_SENT_COMMAND)) {
|
|
host->flags |= FL_SENT_COMMAND;
|
|
at91mci_process_command(host, host->request->cmd);
|
|
}
|
|
else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) {
|
|
host->flags |= FL_SENT_STOP;
|
|
at91mci_process_command(host, host->request->stop);
|
|
}
|
|
else
|
|
mmc_request_done(host->mmc, host->request);
|
|
}
|
|
|
|
/*
|
|
* Handle a command that has been completed
|
|
*/
|
|
static void at91mci_completed_command(struct at91mci_host *host)
|
|
{
|
|
struct mmc_command *cmd = host->cmd;
|
|
unsigned int status;
|
|
|
|
at91_mci_write(AT91_MCI_IDR, 0xffffffff);
|
|
|
|
cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0));
|
|
cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1));
|
|
cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2));
|
|
cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3));
|
|
|
|
if (host->buffer) {
|
|
dma_free_coherent(NULL, host->total_length, host->buffer, host->physical_address);
|
|
host->buffer = NULL;
|
|
}
|
|
|
|
status = at91_mci_read(AT91_MCI_SR);
|
|
|
|
pr_debug("Status = %08X [%08X %08X %08X %08X]\n",
|
|
status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
|
|
|
|
if (status & (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE |
|
|
AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE |
|
|
AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)) {
|
|
if ((status & AT91_MCI_RCRCE) &&
|
|
((cmd->opcode == MMC_SEND_OP_COND) || (cmd->opcode == SD_APP_OP_COND))) {
|
|
cmd->error = MMC_ERR_NONE;
|
|
}
|
|
else {
|
|
if (status & (AT91_MCI_RTOE | AT91_MCI_DTOE))
|
|
cmd->error = MMC_ERR_TIMEOUT;
|
|
else if (status & (AT91_MCI_RCRCE | AT91_MCI_DCRCE))
|
|
cmd->error = MMC_ERR_BADCRC;
|
|
else if (status & (AT91_MCI_OVRE | AT91_MCI_UNRE))
|
|
cmd->error = MMC_ERR_FIFO;
|
|
else
|
|
cmd->error = MMC_ERR_FAILED;
|
|
|
|
pr_debug("Error detected and set to %d (cmd = %d, retries = %d)\n",
|
|
cmd->error, cmd->opcode, cmd->retries);
|
|
}
|
|
}
|
|
else
|
|
cmd->error = MMC_ERR_NONE;
|
|
|
|
at91mci_process_next(host);
|
|
}
|
|
|
|
/*
|
|
* Handle an MMC request
|
|
*/
|
|
static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
|
{
|
|
struct at91mci_host *host = mmc_priv(mmc);
|
|
host->request = mrq;
|
|
host->flags = 0;
|
|
|
|
at91mci_process_next(host);
|
|
}
|
|
|
|
/*
|
|
* Set the IOS
|
|
*/
|
|
static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
{
|
|
int clkdiv;
|
|
struct at91mci_host *host = mmc_priv(mmc);
|
|
unsigned long at91_master_clock = clk_get_rate(mci_clk);
|
|
|
|
host->bus_mode = ios->bus_mode;
|
|
|
|
if (ios->clock == 0) {
|
|
/* Disable the MCI controller */
|
|
at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS);
|
|
clkdiv = 0;
|
|
}
|
|
else {
|
|
/* Enable the MCI controller */
|
|
at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
|
|
|
|
if ((at91_master_clock % (ios->clock * 2)) == 0)
|
|
clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
|
|
else
|
|
clkdiv = (at91_master_clock / ios->clock) / 2;
|
|
|
|
pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv,
|
|
at91_master_clock / (2 * (clkdiv + 1)));
|
|
}
|
|
if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) {
|
|
pr_debug("MMC: Setting controller bus width to 4\n");
|
|
at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
|
|
}
|
|
else {
|
|
pr_debug("MMC: Setting controller bus width to 1\n");
|
|
at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
|
|
}
|
|
|
|
/* Set the clock divider */
|
|
at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
|
|
|
|
/* maybe switch power to the card */
|
|
if (host->board->vcc_pin) {
|
|
switch (ios->power_mode) {
|
|
case MMC_POWER_OFF:
|
|
at91_set_gpio_output(host->board->vcc_pin, 0);
|
|
break;
|
|
case MMC_POWER_UP:
|
|
case MMC_POWER_ON:
|
|
at91_set_gpio_output(host->board->vcc_pin, 1);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Handle an interrupt
|
|
*/
|
|
static irqreturn_t at91_mci_irq(int irq, void *devid)
|
|
{
|
|
struct at91mci_host *host = devid;
|
|
int completed = 0;
|
|
|
|
unsigned int int_status;
|
|
|
|
int_status = at91_mci_read(AT91_MCI_SR);
|
|
pr_debug("MCI irq: status = %08X, %08lX, %08lX\n", int_status, at91_mci_read(AT91_MCI_IMR),
|
|
int_status & at91_mci_read(AT91_MCI_IMR));
|
|
|
|
if ((int_status & at91_mci_read(AT91_MCI_IMR)) & 0xffff0000)
|
|
completed = 1;
|
|
|
|
int_status &= at91_mci_read(AT91_MCI_IMR);
|
|
|
|
if (int_status & AT91_MCI_UNRE)
|
|
pr_debug("MMC: Underrun error\n");
|
|
if (int_status & AT91_MCI_OVRE)
|
|
pr_debug("MMC: Overrun error\n");
|
|
if (int_status & AT91_MCI_DTOE)
|
|
pr_debug("MMC: Data timeout\n");
|
|
if (int_status & AT91_MCI_DCRCE)
|
|
pr_debug("MMC: CRC error in data\n");
|
|
if (int_status & AT91_MCI_RTOE)
|
|
pr_debug("MMC: Response timeout\n");
|
|
if (int_status & AT91_MCI_RENDE)
|
|
pr_debug("MMC: Response end bit error\n");
|
|
if (int_status & AT91_MCI_RCRCE)
|
|
pr_debug("MMC: Response CRC error\n");
|
|
if (int_status & AT91_MCI_RDIRE)
|
|
pr_debug("MMC: Response direction error\n");
|
|
if (int_status & AT91_MCI_RINDE)
|
|
pr_debug("MMC: Response index error\n");
|
|
|
|
/* Only continue processing if no errors */
|
|
if (!completed) {
|
|
if (int_status & AT91_MCI_TXBUFE) {
|
|
pr_debug("TX buffer empty\n");
|
|
at91_mci_handle_transmitted(host);
|
|
}
|
|
|
|
if (int_status & AT91_MCI_RXBUFF) {
|
|
pr_debug("RX buffer full\n");
|
|
at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY);
|
|
}
|
|
|
|
if (int_status & AT91_MCI_ENDTX) {
|
|
pr_debug("Transmit has ended\n");
|
|
}
|
|
|
|
if (int_status & AT91_MCI_ENDRX) {
|
|
pr_debug("Receive has ended\n");
|
|
at91mci_post_dma_read(host);
|
|
}
|
|
|
|
if (int_status & AT91_MCI_NOTBUSY) {
|
|
pr_debug("Card is ready\n");
|
|
at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY);
|
|
}
|
|
|
|
if (int_status & AT91_MCI_DTIP) {
|
|
pr_debug("Data transfer in progress\n");
|
|
}
|
|
|
|
if (int_status & AT91_MCI_BLKE) {
|
|
pr_debug("Block transfer has ended\n");
|
|
}
|
|
|
|
if (int_status & AT91_MCI_TXRDY) {
|
|
pr_debug("Ready to transmit\n");
|
|
}
|
|
|
|
if (int_status & AT91_MCI_RXRDY) {
|
|
pr_debug("Ready to receive\n");
|
|
}
|
|
|
|
if (int_status & AT91_MCI_CMDRDY) {
|
|
pr_debug("Command ready\n");
|
|
completed = 1;
|
|
}
|
|
}
|
|
at91_mci_write(AT91_MCI_IDR, int_status);
|
|
|
|
if (completed) {
|
|
pr_debug("Completed command\n");
|
|
at91_mci_write(AT91_MCI_IDR, 0xffffffff);
|
|
at91mci_completed_command(host);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t at91_mmc_det_irq(int irq, void *_host)
|
|
{
|
|
struct at91mci_host *host = _host;
|
|
int present = !at91_get_gpio_value(irq);
|
|
|
|
/*
|
|
* we expect this irq on both insert and remove,
|
|
* and use a short delay to debounce.
|
|
*/
|
|
if (present != host->present) {
|
|
host->present = present;
|
|
pr_debug("%s: card %s\n", mmc_hostname(host->mmc),
|
|
present ? "insert" : "remove");
|
|
if (!present) {
|
|
pr_debug("****** Resetting SD-card bus width ******\n");
|
|
at91_mci_write(AT91_MCI_SDCR, 0);
|
|
}
|
|
mmc_detect_change(host->mmc, msecs_to_jiffies(100));
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
int at91_mci_get_ro(struct mmc_host *mmc)
|
|
{
|
|
int read_only = 0;
|
|
struct at91mci_host *host = mmc_priv(mmc);
|
|
|
|
if (host->board->wp_pin) {
|
|
read_only = at91_get_gpio_value(host->board->wp_pin);
|
|
printk(KERN_WARNING "%s: card is %s\n", mmc_hostname(mmc),
|
|
(read_only ? "read-only" : "read-write") );
|
|
}
|
|
else {
|
|
printk(KERN_WARNING "%s: host does not support reading read-only "
|
|
"switch. Assuming write-enable.\n", mmc_hostname(mmc));
|
|
}
|
|
return read_only;
|
|
}
|
|
|
|
static struct mmc_host_ops at91_mci_ops = {
|
|
.request = at91_mci_request,
|
|
.set_ios = at91_mci_set_ios,
|
|
.get_ro = at91_mci_get_ro,
|
|
};
|
|
|
|
/*
|
|
* Probe for the device
|
|
*/
|
|
static int at91_mci_probe(struct platform_device *pdev)
|
|
{
|
|
struct mmc_host *mmc;
|
|
struct at91mci_host *host;
|
|
int ret;
|
|
|
|
pr_debug("Probe MCI devices\n");
|
|
at91_mci_disable();
|
|
at91_mci_enable();
|
|
|
|
mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev);
|
|
if (!mmc) {
|
|
pr_debug("Failed to allocate mmc host\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
mmc->ops = &at91_mci_ops;
|
|
mmc->f_min = 375000;
|
|
mmc->f_max = 25000000;
|
|
mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
mmc->caps = MMC_CAP_BYTEBLOCK;
|
|
|
|
host = mmc_priv(mmc);
|
|
host->mmc = mmc;
|
|
host->buffer = NULL;
|
|
host->bus_mode = 0;
|
|
host->board = pdev->dev.platform_data;
|
|
if (host->board->wire4) {
|
|
#ifdef SUPPORT_4WIRE
|
|
mmc->caps |= MMC_CAP_4_BIT_DATA;
|
|
#else
|
|
printk("MMC: 4 wire bus mode not supported by this driver - using 1 wire\n");
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Get Clock
|
|
*/
|
|
mci_clk = clk_get(&pdev->dev, "mci_clk");
|
|
if (IS_ERR(mci_clk)) {
|
|
printk(KERN_ERR "AT91 MMC: no clock defined.\n");
|
|
mmc_free_host(mmc);
|
|
return -ENODEV;
|
|
}
|
|
clk_enable(mci_clk); /* Enable the peripheral clock */
|
|
|
|
/*
|
|
* Allocate the MCI interrupt
|
|
*/
|
|
ret = request_irq(AT91RM9200_ID_MCI, at91_mci_irq, IRQF_SHARED, DRIVER_NAME, host);
|
|
if (ret) {
|
|
printk(KERN_ERR "Failed to request MCI interrupt\n");
|
|
clk_disable(mci_clk);
|
|
clk_put(mci_clk);
|
|
mmc_free_host(mmc);
|
|
return ret;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, mmc);
|
|
|
|
/*
|
|
* Add host to MMC layer
|
|
*/
|
|
if (host->board->det_pin)
|
|
host->present = !at91_get_gpio_value(host->board->det_pin);
|
|
else
|
|
host->present = -1;
|
|
|
|
mmc_add_host(mmc);
|
|
|
|
/*
|
|
* monitor card insertion/removal if we can
|
|
*/
|
|
if (host->board->det_pin) {
|
|
ret = request_irq(host->board->det_pin, at91_mmc_det_irq,
|
|
0, DRIVER_NAME, host);
|
|
if (ret)
|
|
printk(KERN_ERR "couldn't allocate MMC detect irq\n");
|
|
}
|
|
|
|
pr_debug(KERN_INFO "Added MCI driver\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Remove a device
|
|
*/
|
|
static int at91_mci_remove(struct platform_device *pdev)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(pdev);
|
|
struct at91mci_host *host;
|
|
|
|
if (!mmc)
|
|
return -1;
|
|
|
|
host = mmc_priv(mmc);
|
|
|
|
if (host->present != -1) {
|
|
free_irq(host->board->det_pin, host);
|
|
cancel_delayed_work(&host->mmc->detect);
|
|
}
|
|
|
|
mmc_remove_host(mmc);
|
|
at91_mci_disable();
|
|
free_irq(AT91RM9200_ID_MCI, host);
|
|
mmc_free_host(mmc);
|
|
|
|
clk_disable(mci_clk); /* Disable the peripheral clock */
|
|
clk_put(mci_clk);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
pr_debug("MCI Removed\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(pdev);
|
|
int ret = 0;
|
|
|
|
if (mmc)
|
|
ret = mmc_suspend_host(mmc, state);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int at91_mci_resume(struct platform_device *pdev)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(pdev);
|
|
int ret = 0;
|
|
|
|
if (mmc)
|
|
ret = mmc_resume_host(mmc);
|
|
|
|
return ret;
|
|
}
|
|
#else
|
|
#define at91_mci_suspend NULL
|
|
#define at91_mci_resume NULL
|
|
#endif
|
|
|
|
static struct platform_driver at91_mci_driver = {
|
|
.probe = at91_mci_probe,
|
|
.remove = at91_mci_remove,
|
|
.suspend = at91_mci_suspend,
|
|
.resume = at91_mci_resume,
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init at91_mci_init(void)
|
|
{
|
|
return platform_driver_register(&at91_mci_driver);
|
|
}
|
|
|
|
static void __exit at91_mci_exit(void)
|
|
{
|
|
platform_driver_unregister(&at91_mci_driver);
|
|
}
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module_init(at91_mci_init);
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module_exit(at91_mci_exit);
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|
|
|
MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver");
|
|
MODULE_AUTHOR("Nick Randell");
|
|
MODULE_LICENSE("GPL");
|