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be338e4c58
A83T has similar bus gates that of H3, including single gating register has different clock parent. As per H3 and A83T datasheet, usbhost is under AHB2. However,below shows allwinner source code assignment: bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T. bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3 bits 29, 30, 31(ohci0,1,2) => AHB2 for H3. until, this confusion is cleared keep it H3 way. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
113 lines
3.1 KiB
C
113 lines
3.1 KiB
C
/*
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* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
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*
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* Based on clk-simple-gates.c, which is:
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* Copyright 2015 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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static DEFINE_SPINLOCK(gates_lock);
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static void __init sun8i_h3_bus_gates_init(struct device_node *node)
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{
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static const char * const names[] = { "ahb1", "ahb2", "apb1", "apb2" };
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enum { AHB1, AHB2, APB1, APB2, PARENT_MAX } clk_parent;
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const char *parents[PARENT_MAX];
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struct clk_onecell_data *clk_data;
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const char *clk_name;
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struct property *prop;
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struct resource res;
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void __iomem *clk_reg;
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void __iomem *reg;
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const __be32 *p;
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int number, i;
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u8 clk_bit;
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int index;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (IS_ERR(reg))
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return;
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for (i = 0; i < ARRAY_SIZE(names); i++) {
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int idx = of_property_match_string(node, "clock-names",
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names[i]);
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if (idx < 0)
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return;
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parents[i] = of_clk_get_parent_name(node, idx);
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}
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clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
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if (!clk_data)
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goto err_unmap;
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number = of_property_count_u32_elems(node, "clock-indices");
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of_property_read_u32_index(node, "clock-indices", number - 1, &number);
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clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
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if (!clk_data->clks)
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goto err_free_data;
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i = 0;
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of_property_for_each_u32(node, "clock-indices", prop, p, index) {
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of_property_read_string_index(node, "clock-output-names",
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i, &clk_name);
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if (index == 17 || (index >= 29 && index <= 31))
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clk_parent = AHB2;
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else if (index <= 63 || index >= 128)
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clk_parent = AHB1;
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else if (index >= 64 && index <= 95)
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clk_parent = APB1;
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else if (index >= 96 && index <= 127)
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clk_parent = APB2;
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clk_reg = reg + 4 * (index / 32);
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clk_bit = index % 32;
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clk_data->clks[index] = clk_register_gate(NULL, clk_name,
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parents[clk_parent],
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0, clk_reg, clk_bit,
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0, &gates_lock);
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i++;
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if (IS_ERR(clk_data->clks[index])) {
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WARN_ON(true);
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continue;
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}
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}
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clk_data->clk_num = number + 1;
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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return;
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err_free_data:
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kfree(clk_data);
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err_unmap:
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iounmap(reg);
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of_address_to_resource(node, 0, &res);
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release_mem_region(res.start, resource_size(&res));
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}
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CLK_OF_DECLARE(sun8i_h3_bus_gates, "allwinner,sun8i-h3-bus-gates-clk",
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sun8i_h3_bus_gates_init);
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CLK_OF_DECLARE(sun8i_a83t_bus_gates, "allwinner,sun8i-a83t-bus-gates-clk",
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sun8i_h3_bus_gates_init);
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