150 lines
4.0 KiB
YAML
150 lines
4.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx NWL PCIe Root Port Bridge
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maintainers:
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- Thippeswamy Havalige <thippeswamy.havalige@amd.com>
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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- $ref: /schemas/interrupt-controller/msi-controller.yaml#
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properties:
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compatible:
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const: xlnx,nwl-pcie-2.11
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reg:
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items:
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- description: PCIe bridge registers location.
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- description: PCIe Controller registers location.
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- description: PCIe Configuration space region.
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reg-names:
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items:
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- const: breg
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- const: pcireg
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- const: cfg
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interrupts:
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items:
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- description: interrupt asserted when miscellaneous interrupt is received
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- description: unused interrupt(dummy)
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- description: interrupt asserted when a legacy interrupt is received
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- description: msi1 interrupt asserted when an MSI is received
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- description: msi0 interrupt asserted when an MSI is received
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interrupt-names:
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items:
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- const: misc
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- const: dummy
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- const: intx
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- const: msi1
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- const: msi0
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interrupt-map-mask:
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items:
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- const: 0
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- const: 0
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- const: 0
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- const: 7
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"#interrupt-cells":
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const: 1
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msi-parent:
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description: MSI controller the device is capable of using.
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interrupt-map:
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maxItems: 4
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power-domains:
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maxItems: 1
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iommus:
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maxItems: 1
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dma-coherent:
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description: optional, only needed if DMA operations are coherent.
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clocks:
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maxItems: 1
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description: optional, input clock specifier.
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legacy-interrupt-controller:
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description: Interrupt controller node for handling legacy PCI interrupts.
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type: object
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properties:
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"#address-cells":
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const: 0
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"#interrupt-cells":
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const: 1
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"interrupt-controller": true
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required:
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- "#address-cells"
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- "#interrupt-cells"
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- interrupt-controller
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additionalProperties: false
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- "#interrupt-cells"
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- interrupt-map
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- interrupt-map-mask
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- msi-controller
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- power-domains
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/xlnx-zynqmp-power.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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nwl_pcie: pcie@fd0e0000 {
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compatible = "xlnx,nwl-pcie-2.11";
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reg = <0x0 0xfd0e0000 0x0 0x1000>,
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<0x0 0xfd480000 0x0 0x1000>,
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<0x80 0x00000000 0x0 0x10000000>;
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reg-names = "breg", "pcireg", "cfg";
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ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
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<0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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msi-controller;
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device_type = "pci";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "misc", "dummy", "intx", "msi1", "msi0";
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
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<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
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<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
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<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
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msi-parent = <&nwl_pcie>;
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power-domains = <&zynqmp_firmware PD_PCIE>;
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iommus = <&smmu 0x4d0>;
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pcie_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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