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0934eec7bc
We already had an earlier conclusion that all new i.MX Socs will keep using the legacy i.MX Pinctrl bindings instead of generic pin config. However, MX7ULP generic pin config binding support has already been in tree before that time. Per SoC maintainers' suggestions, in order to get a better consistency for all i.MX devices, we'd like to go back to imx legacy binding for MX7ULP as well. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Stefan Agner <stefan@agner.ch> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: linux-gpio@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
53 lines
1.4 KiB
Text
53 lines
1.4 KiB
Text
* Freescale i.MX7ULP IOMUX Controller
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i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
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ports and IOMUXC DDR for DDR interface.
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Note:
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This binding doc is only for the IOMUXC1 support in A7 Domain and it only
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supports generic pin config.
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Please refer to fsl,imx-pinctrl.txt in this directory for common binding
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part and usage.
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Required properties:
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- compatible: "fsl,imx7ulp-iomuxc1".
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- fsl,pins: Each entry consists of 5 integers which represents the mux
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and config setting for one pin. The first 4 integers
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<mux_conf_reg input_reg mux_mode input_val> are specified
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using a PIN_FUNC_ID macro, which can be found in
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imx7ulp-pinfunc.h in the device tree source folder.
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The last integer CONFIG is the pad setting value like
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pull-up on this pin.
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Please refer to i.MX7ULP Reference Manual for detailed
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CONFIG settings.
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CONFIG bits definition:
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PAD_CTL_OBE (1 << 17)
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PAD_CTL_IBE (1 << 16)
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PAD_CTL_LK (1 << 16)
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PAD_CTL_DSE_HI (1 << 6)
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PAD_CTL_DSE_STD (0 << 6)
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PAD_CTL_ODE (1 << 5)
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PAD_CTL_PUSH_PULL (0 << 5)
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PAD_CTL_SRE_SLOW (1 << 2)
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PAD_CTL_SRE_STD (0 << 2)
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PAD_CTL_PE (1 << 0)
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Examples:
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#include "imx7ulp-pinfunc.h"
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/* Pin Controller Node */
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iomuxc1: pinctrl@40ac0000 {
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compatible = "fsl,imx7ulp-iomuxc1";
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reg = <0x40ac0000 0x1000>;
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/* Pin Configuration Node */
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pinctrl_lpuart4: lpuart4grp {
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fsl,pins = <
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IMX7ULP_PAD_PTC3__LPUART4_RX 0x1
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IMX7ULP_PAD_PTC2__LPUART4_TX 0x1
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>;
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};
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};
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