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2bdcdad693
Just as unevaluatedProperties or additionalProperties are required at the top level of schemas, they should (and will) also be required for child node schemas. That ensures only documented properties are present for any node. Add the missing addtionalProperties to the 'gpio' child nodes. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231020170017.3610978-1-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
217 lines
6.4 KiB
YAML
217 lines
6.4 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/nuvoton,npcm845-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Nuvoton NPCM845 Pin Controller and GPIO
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maintainers:
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- Tomer Maimon <tmaimon77@gmail.com>
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description:
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The Nuvoton BMC NPCM8XX Pin Controller multi-function routed through
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the multiplexing block, Each pin supports GPIO functionality (GPIOx)
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and multiple functions that directly connect the pin to different
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hardware blocks.
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properties:
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compatible:
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const: nuvoton,npcm845-pinctrl
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ranges:
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maxItems: 1
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'#address-cells':
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const: 1
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'#size-cells':
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const: 1
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nuvoton,sysgcr:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: a phandle to access GCR registers.
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patternProperties:
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'^gpio@':
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type: object
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additionalProperties: false
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description:
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Eight GPIO banks that each contain 32 GPIOs.
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properties:
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gpio-controller: true
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'#gpio-cells':
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const: 2
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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gpio-ranges:
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maxItems: 1
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required:
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- gpio-controller
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- '#gpio-cells'
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- reg
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- interrupts
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- gpio-ranges
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'-mux$':
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$ref: pinmux-node.yaml#
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properties:
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groups:
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description:
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One or more groups of pins to mux to a certain function
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items:
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enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
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smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b,
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smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21,
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smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3,
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spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2,
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spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2,
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bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen,
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r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3,
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fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
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fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
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pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
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ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
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smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
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sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
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mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
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scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1,
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spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den,
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smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix,
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spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
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hgpio5, hgpio6, hgpio7 ]
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function:
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description:
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The function that a group of pins is muxed to
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enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
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smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b,
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smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21,
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smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3,
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spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2,
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spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2,
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bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen,
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r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3,
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fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
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fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
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pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
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ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
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smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
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sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
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mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
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scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1,
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spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den,
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smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix,
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spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
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hgpio5, hgpio6, hgpio7 ]
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dependencies:
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groups: [ function ]
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function: [ groups ]
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additionalProperties: false
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'^pin':
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$ref: pincfg-node.yaml#
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properties:
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pins:
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description:
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A list of pins to configure in certain ways, such as enabling
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debouncing
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items:
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pattern: '^GPIO([0-9]|[0-9][0-9]|1[0-9][0-9]|2[0-4][0-9]|25[0-6])'
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bias-disable: true
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bias-pull-up: true
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bias-pull-down: true
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input-enable: true
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output-low: true
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output-high: true
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drive-push-pull: true
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drive-open-drain: true
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input-debounce:
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description:
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Debouncing periods in microseconds, one period per interrupt
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bank found in the controller
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 4
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slew-rate:
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description: |
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0: Low rate
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1: High rate
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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drive-strength:
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enum: [ 0, 1, 2, 4, 8, 12 ]
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additionalProperties: false
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allOf:
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- $ref: pinctrl.yaml#
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required:
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- compatible
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- ranges
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- '#address-cells'
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- '#size-cells'
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- nuvoton,sysgcr
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pinctrl: pinctrl@f0010000 {
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compatible = "nuvoton,npcm845-pinctrl";
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ranges = <0x0 0x0 0xf0010000 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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nuvoton,sysgcr = <&gcr>;
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gpio0: gpio@0 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x0 0xb0>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&pinctrl 0 0 32>;
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};
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fanin0_pin: fanin0-mux {
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groups = "fanin0";
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function = "fanin0";
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};
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pin34_slew: pin34-slew {
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pins = "GPIO34/I3C4_SDA";
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bias-disable;
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};
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};
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};
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