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d3e591a38c
Following the examples of cbom-block-size and cboz-block-size, cbop-block-size is the cache size of Zicbop (cbo.prefetch) operations. The most common case is to have all cache block sizes to be the same size (e.g. profiles such as rva22u64 mandates a 64 bytes size for all cache operations), but there's no specification requirement for that, and an implementation can have different cache sizes for each operation. Cc: Rob Herring <robh@kernel.org> Cc: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20231029123500.739409-1-dbarboza@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
219 lines
6.2 KiB
YAML
219 lines
6.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR MIT)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/riscv/cpus.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: RISC-V CPUs
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maintainers:
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- Paul Walmsley <paul.walmsley@sifive.com>
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- Palmer Dabbelt <palmer@sifive.com>
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- Conor Dooley <conor@kernel.org>
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description: |
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This document uses some terminology common to the RISC-V community
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that is not widely used, the definitions of which are listed here:
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hart: A hardware execution context, which contains all the state
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mandated by the RISC-V ISA: a PC and some registers. This
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terminology is designed to disambiguate software's view of execution
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contexts from any particular microarchitectural implementation
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strategy. For example, an Intel laptop containing one socket with
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two cores, each of which has two hyperthreads, could be described as
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having four harts.
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allOf:
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- $ref: /schemas/cpu.yaml#
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- $ref: extensions.yaml
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- amd,mbv32
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- andestech,ax45mp
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- canaan,k210
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- sifive,bullet0
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- sifive,e5
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- sifive,e7
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- sifive,e71
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- sifive,rocket0
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- sifive,s7
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- sifive,u5
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- sifive,u54
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- sifive,u7
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- sifive,u74
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- sifive,u74-mc
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- thead,c906
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- thead,c910
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- thead,c920
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- const: riscv
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- items:
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- enum:
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- sifive,e51
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- sifive,u54-mc
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- const: sifive,rocket0
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- const: riscv
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- const: riscv # Simulator only
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description:
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Identifies that the hart uses the RISC-V instruction set
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and identifies the type of the hart.
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mmu-type:
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description:
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Identifies the largest MMU address translation mode supported by
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this hart. These values originate from the RISC-V Privileged
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Specification document, available from
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https://riscv.org/specifications/
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$ref: /schemas/types.yaml#/definitions/string
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enum:
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- riscv,sv32
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- riscv,sv39
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- riscv,sv48
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- riscv,sv57
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- riscv,none
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riscv,cbom-block-size:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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The blocksize in bytes for the Zicbom cache operations.
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riscv,cbop-block-size:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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The blocksize in bytes for the Zicbop cache operations.
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riscv,cboz-block-size:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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The blocksize in bytes for the Zicboz cache operations.
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# RISC-V has multiple properties for cache op block sizes as the sizes
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# differ between individual CBO extensions
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cache-op-block-size: false
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# RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
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timebase-frequency: false
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interrupt-controller:
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type: object
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additionalProperties: false
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description: Describes the CPU's local interrupt controller
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properties:
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'#interrupt-cells':
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const: 1
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compatible:
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const: riscv,cpu-intc
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interrupt-controller: true
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required:
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- '#interrupt-cells'
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- compatible
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- interrupt-controller
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cpu-idle-states:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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maxItems: 1
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description: |
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List of phandles to idle state nodes supported
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by this hart (see ./idle-states.yaml).
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capacity-dmips-mhz:
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description:
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u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
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DMIPS/MHz, relative to highest capacity-dmips-mhz
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in the system.
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anyOf:
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- required:
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- riscv,isa
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- required:
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- riscv,isa-base
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dependencies:
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riscv,isa-base: [ "riscv,isa-extensions" ]
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riscv,isa-extensions: [ "riscv,isa-base" ]
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required:
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- interrupt-controller
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unevaluatedProperties: false
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examples:
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- |
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// Example 1: SiFive Freedom U540G Development Kit
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <1000000>;
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cpu@0 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <16384>;
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reg = <0>;
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "c";
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cpu_intc0: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@1 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <1>;
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tlb-split;
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
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cpu_intc1: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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- |
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// Example 2: Spike ISA Simulator with 1 Hart
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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reg = <0>;
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compatible = "riscv";
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mmu-type = "riscv,sv48";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
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interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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...
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